component statements within architecture statements

Discussion in 'VHDL' started by Neil Zanella, Oct 16, 2003.

  1. Neil Zanella

    Neil Zanella Guest

    Hello,

    I would like to ask a question concerning the intended use of component
    statements within architecture statements in VHDL. Since when
    instantiating different components the component part is optional, why
    would anyone want to include it. Even if two entities were defined with an
    interface with clashing signal names, the scope of those names would not
    interfere when those entities are used for instantiation. So why would
    anyone want to use an explicit component statement inside an architecture?

    Thanks,

    Neil
    Neil Zanella, Oct 16, 2003
    #1
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  2. Neil Zanella wrote:

    > I would like to ask a question concerning the intended use of component
    > statements within architecture statements in VHDL. Since when
    > instantiating different components the component part is optional, why
    > would anyone want to include it. Even if two entities were defined with an
    > interface with clashing signal names, the scope of those names would not
    > interfere when those entities are used for instantiation. So why would
    > anyone want to use an explicit component statement inside an architecture?


    A component is a socket into which you can plug
    any entity/architecture that fits using a configuration.

    If there will only be one such module to plug in,
    as is often the case, then direct instances
    without component declarations make sense.

    However, if you expect to plug in a different module in
    the future, an indirect instance now may simplify
    the future change while providing backward compatibility
    with the first design.

    -- Mike Treseler
    Mike Treseler, Oct 17, 2003
    #2
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  3. Neil Zanella

    Barry Brown Guest

    So what is the correct syntax for instantiating an entity that is not in
    your "work" library? I've never been able to figure out direct
    instantiation of Xilinx unisim primitives - either ModelSim or Synplify (or
    both) choke on everything I've tried. It seems like this should work...

    library unisim;
    use unisim.vcomponents.all;

    ....

    Mult1 : entity unisim.MULT18X18
    port map (P => P2, A => a(k,2), B => w0slv);

    Thanks,
    Barry Brown


    "Mike Treseler" <> wrote in message
    news:...
    >
    >
    > Neil Zanella wrote:
    >
    > > I would like to ask a question concerning the intended use of component
    > > statements within architecture statements in VHDL. Since when
    > > instantiating different components the component part is optional, why
    > > would anyone want to include it. Even if two entities were defined with

    an
    > > interface with clashing signal names, the scope of those names would not
    > > interfere when those entities are used for instantiation. So why would
    > > anyone want to use an explicit component statement inside an

    architecture?
    >
    > A component is a socket into which you can plug
    > any entity/architecture that fits using a configuration.
    >
    > If there will only be one such module to plug in,
    > as is often the case, then direct instances
    > without component declarations make sense.
    >
    > However, if you expect to plug in a different module in
    > the future, an indirect instance now may simplify
    > the future change while providing backward compatibility
    > with the first design.
    >
    > -- Mike Treseler
    >
    Barry Brown, Oct 17, 2003
    #3
  4. I do it like this (example: a simple wrapper for the Xilinx ROC
    primitive). XST seems smart enough to secan the named libraries (in
    addition to work) to find ROC.

    LIBRARY ieee ;
    USE ieee.std_logic_1164.all;

    ENTITY XROC IS
    PORT(
    O : OUT std_ulogic
    );
    END XROC ;

    library ieee;
    use ieee.std_logic_1164.all;
    library unisim;
    use unisim.VCOMPONENTS.all; -- Xilinx primitives

    architecture xilinx of XROC is

    begin
    croc : component ROC -- Reset on Configuration
    port map (
    O => O);

    end xilinx;

    "Barry Brown" <> wrote:

    :So what is the correct syntax for instantiating an entity that is not in
    :your "work" library? I've never been able to figure out direct
    :instantiation of Xilinx unisim primitives - either ModelSim or Synplify (or
    :both) choke on everything I've tried. It seems like this should work...
    :
    :library unisim;
    :use unisim.vcomponents.all;
    :
    :...
    :
    : Mult1 : entity unisim.MULT18X18
    : port map (P => P2, A => a(k,2), B => w0slv);
    :
    :Thanks,
    :Barry Brown
    :
    :
    :"Mike Treseler" <> wrote in message
    :news:...
    :>
    :>
    :> Neil Zanella wrote:
    :>
    :> > I would like to ask a question concerning the intended use of component
    :> > statements within architecture statements in VHDL. Since when
    :> > instantiating different components the component part is optional, why
    :> > would anyone want to include it. Even if two entities were defined with
    :an
    :> > interface with clashing signal names, the scope of those names would not
    :> > interfere when those entities are used for instantiation. So why would
    :> > anyone want to use an explicit component statement inside an
    :architecture?
    :>
    :> A component is a socket into which you can plug
    :> any entity/architecture that fits using a configuration.
    :>
    :> If there will only be one such module to plug in,
    :> as is often the case, then direct instances
    :> without component declarations make sense.
    :>
    :> However, if you expect to plug in a different module in
    :> the future, an indirect instance now may simplify
    :> the future change while providing backward compatibility
    :> with the first design.
    :>
    :> -- Mike Treseler
    :>
    :
    David R Brooks, Oct 18, 2003
    #4
  5. Neil Zanella

    Duane Clark Guest

    Barry Brown wrote:
    > So what is the correct syntax for instantiating an entity that is not in
    > your "work" library? I've never been able to figure out direct
    > instantiation of Xilinx unisim primitives - either ModelSim or Synplify (or
    > both) choke on everything I've tried. It seems like this should work...
    >


    I use this, which works in both Synplify and Modelsim:

    --synopsys translate_off;
    LIBRARY UNISIM;
    USE UNISIM.Vcomponents.ALL;
    --synopsys translate_on;
    library synplify;
    use synplify.attributes.all;

    ARCHITECTURE synth OF tmux IS
    component ROC
    port (
    O : out std_logic
    );
    end component;
    -- Synplify attributes
    attribute syn_black_box of ROC : component is true;
    BEGIN
    TRST : ROC
    port map(O => reset);


    --
    My real email is akamail.com@dclark (or something like that).
    Duane Clark, Oct 18, 2003
    #5
  6. Neil Zanella

    Neil Zanella Guest

    Duane Clark <> wrote in message:

    > ARCHITECTURE synth OF tmux IS
    > component ROC
    > port (
    > O : out std_logic
    > );


    .... so why is it that VHDL requires the port section to be copied from the
    entity declaration to the component declaration? Can't VHDL figure the
    information out based on component name matching looking for an entity
    that has the same name and using the names from the port section
    specified therein?

    Thanks,

    Neil

    > end component;
    > -- Synplify attributes
    > attribute syn_black_box of ROC : component is true;
    > BEGIN
    > TRST : ROC
    > port map(O => reset);
    Neil Zanella, Oct 19, 2003
    #6
  7. Neil Zanella

    Duane Clark Guest

    Neil Zanella wrote:
    >
    > ... so why is it that VHDL requires the port section to be copied from the
    > entity declaration to the component declaration? Can't VHDL figure the
    > information out based on component name matching looking for an entity
    > that has the same name and using the names from the port section
    > specified therein?
    >


    I am in the habit of putting explicit component declarations into code
    to be synthesized, but not into testbench code. Don't really know how I
    got into that habit, and really haven't had a reason to change.

    --
    My real email is akamail.com@dclark (or something like that).
    Duane Clark, Oct 19, 2003
    #7
  8. Neil Zanella wrote:

    > ... so why is it that VHDL requires the port section to be copied from the
    > entity declaration to the component declaration? Can't VHDL figure the
    > information out based on component name matching looking for an entity
    > that has the same name and using the names from the port section
    > specified therein?


    A component is an *optional* interface specification
    that allows the compiler to complain if a referenced
    entity does not match the template. The information
    is necessarily redundant, but it is easy work for
    many vhdl editors. For emacs menus it's

    click, VHDL, PORT, COPY
    click, VHDL, PORT, PASTE AS COMP

    -- Mike Treseler
    Mike Treseler, Oct 19, 2003
    #8
  9. Neil Zanella

    mfmehdi

    Joined:
    Sep 24, 2006
    Messages:
    2
    Location:
    iran
    hi all
    i can drire lcd with fpga . can you help me ?
    thanks
    mfmehdi, Oct 20, 2006
    #9
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