Connecting inout signal to out.

Discussion in 'VHDL' started by pallav, May 3, 2008.

  1. pallav

    pallav Guest

    I have a tool that generated the following code for a nand2 schematic
    (static CMOS) in VHDL. When I compile it (GHDL), I get errors
    indicating that I'm trying to connect an inout port to an out port.
    Can some tell me how I can resolve this error without making y an
    'inout' port. Thanks for any help.

    x.vhd:21:41: cannot associate inout signal interface "d" with actual
    port of mode out
    x.vhd:22:33: cannot associate inout signal interface "s" with actual
    port of mode out
    x.vhd:23:33: cannot associate inout signal interface "s" with actual
    port of mode out

    -- VHDL automatically generated by Electric 8.06 for cell 'nand2{sch}'
    entity nand2 is port(a, b: in BIT; y: out BIT);
    end nand2;

    architecture nand2_BODY of nand2 is
    component ground port(gnd: out BIT);
    end component;
    component nMOStran port(g: in BIT; s, d: inout BIT);
    end component;
    component PMOStran port(g: in BIT; s, d: inout BIT);
    end component;
    component power port(vdd: out BIT);
    end component;

    signal gnd, vdd, net_52: BIT;

    begin
    gnd_1: ground port map(gnd);
    nmos_3: nMOStran port map(b, gnd, net_52);
    nmos_4: nMOStran port map(a, net_52, y); <-- signal y
    pmos_2: PMOStran port map(a, y, vdd); <-- signal y
    pmos_3: PMOStran port map(b, y, vdd); <-- signal y
    pwr_0: power port map(vdd);
    end nand2_BODY;
     
    pallav, May 3, 2008
    #1
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  2. pallav

    pallav Guest

    On May 3, 6:02 pm, pallav <> wrote:
    > I have a tool that generated the following code for a nand2 schematic
    > (static CMOS) in VHDL. When I compile it (GHDL), I get errors
    > indicating that I'm trying to connect an inout port to an out port.
    > Can some tell me how I can resolve this error without making y an
    > 'inout' port. Thanks for any help.
    >
    > x.vhd:21:41: cannot associate inout signal interface "d" with actual
    > port of mode out
    > x.vhd:22:33: cannot associate inout signal interface "s" with actual
    > port of mode out
    > x.vhd:23:33: cannot associate inout signal interface "s" with actual
    > port of mode out
    >
    > -- VHDL automatically generated by Electric 8.06 for cell 'nand2{sch}'
    > entity nand2 is port(a, b: in BIT; y: out BIT);
    >   end nand2;
    >
    > architecture nand2_BODY of nand2 is
    >   component ground port(gnd: out BIT);
    >     end component;
    >   component nMOStran port(g: in BIT; s, d: inout BIT);
    >     end component;
    >   component PMOStran port(g: in BIT; s, d: inout BIT);
    >     end component;
    >   component power port(vdd: out BIT);
    >     end component;
    >
    >   signal gnd, vdd, net_52: BIT;
    >
    > begin
    >   gnd_1: ground port map(gnd);
    >   nmos_3: nMOStran port map(b, gnd, net_52);
    >   nmos_4: nMOStran port map(a, net_52, y); <-- signal y
    >   pmos_2: PMOStran port map(a, y, vdd);  <-- signal y
    >   pmos_3: PMOStran port map(b, y, vdd); <-- signal y
    >   pwr_0: power port map(vdd);
    > end nand2_BOD


    Actually, a follow-up question. Does VHDL have nmos/pmos transistor
    definitions like Verilog does?
    I haven't been able to find anything on the VHDL reference cards. I'm
    wondering if nMOStran/PMOStran are pre-defined in VHDL or part of some
    package? If not, then perhaps the above question is not of importance
    as it might be a peculiarity of the tool that I'm using. Will look
    into its documentation.
     
    pallav, May 3, 2008
    #2
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  3. pallav

    pallav Guest

    On May 3, 6:33 pm, pallav <> wrote:
    > On May 3, 6:02 pm, pallav <> wrote:
    >
    >
    >
    > > I have a tool that generated the following code for a nand2 schematic
    > > (static CMOS) in VHDL. When I compile it (GHDL), I get errors
    > > indicating that I'm trying to connect an inout port to an out port.
    > > Can some tell me how I can resolve this error without making y an
    > > 'inout' port. Thanks for any help.

    >
    > > x.vhd:21:41: cannot associate inout signal interface "d" with actual
    > > port of mode out
    > > x.vhd:22:33: cannot associate inout signal interface "s" with actual
    > > port of mode out
    > > x.vhd:23:33: cannot associate inout signal interface "s" with actual
    > > port of mode out

    >
    > > -- VHDL automatically generated by Electric 8.06 for cell 'nand2{sch}'
    > > entity nand2 is port(a, b: in BIT; y: out BIT);
    > >   end nand2;

    >
    > > architecture nand2_BODY of nand2 is
    > >   component ground port(gnd: out BIT);
    > >     end component;
    > >   component nMOStran port(g: in BIT; s, d: inout BIT);
    > >     end component;
    > >   component PMOStran port(g: in BIT; s, d: inout BIT);
    > >     end component;
    > >   component power port(vdd: out BIT);
    > >     end component;

    >
    > >   signal gnd, vdd, net_52: BIT;

    >
    > > begin
    > >   gnd_1: ground port map(gnd);
    > >   nmos_3: nMOStran port map(b, gnd, net_52);
    > >   nmos_4: nMOStran port map(a, net_52, y); <-- signal y
    > >   pmos_2: PMOStran port map(a, y, vdd);  <-- signal y
    > >   pmos_3: PMOStran port map(b, y, vdd); <-- signal y
    > >   pwr_0: power port map(vdd);
    > > end nand2_BOD

    >
    > Actually, a follow-up question. Does VHDL have nmos/pmos transistor
    > definitions like Verilog does?
    > I haven't been able to find anything on the VHDL reference cards. I'm
    > wondering if nMOStran/PMOStran are pre-defined in VHDL or part of some
    > package? If not, then perhaps the above question is not of importance
    > as it might be a peculiarity of the tool that I'm using. Will look
    > into its documentation.


    Please ignore the above OP. Its not relevant anymore.
     
    pallav, May 3, 2008
    #3
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