connecting std_logic inout ports and std_logic_vector inout port

Discussion in 'VHDL' started by =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=, Nov 6, 2007.

  1. Hi,

    I'm looking for a (nice) way to connect std_logic_vector and several
    std_logic in order to avoid modifying UCF files in ISE.

    My simplified problem:
    I have a top entity with two "inout" ports (let's say Data_0 and Data_1)
    with type std_logic.
    I want to map these two signals on an "inout" port of a component with
    type std_logic_vector(1 downto 0).

    My first idea was to use an alias, but I can't make it work. I tried
    several ways:
    - alias Data : std_logic_vector(1 downto 0) is (Data_0, Data_1);
    - alias Data : std_logic_vector(1 downto 0) is (Data_0 & Data_1);
    - alias Data : std_logic_vector(1 downto 0) is Data_0, Data_1;
    - alias Data : std_logic_vector(1 downto 0) is Data_0 & Data_1;
    ISE gives me an error in every case.

    My second idea was to map directly.
    port map ( Data => Data_0 & Data_1);
    But ISE doesn't want to do that with inout ports.


    For now, I'm lacking of ideas because I would really appreciate to solve
    this issue without modifying my top entity.

    Thanks in advance.
     
    =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=, Nov 6, 2007
    #1
    1. Advertising

  2. =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=

    Duane Clark Guest

    Frédéric Lochon wrote:
    >
    > My second idea was to map directly.
    > port map ( Data => Data_0 & Data_1);


    port map ( Data(0) => Data_0, Data(1) => Data_1 );
     
    Duane Clark, Nov 6, 2007
    #2
    1. Advertising

  3. =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=

    Tricky Guest

    On Nov 6, 10:03 pm, Duane Clark <> wrote:
    > Frédéric Lochon wrote:
    >
    > > My second idea was to map directly.
    > > port map ( Data => Data_0 & Data_1);

    >
    > port map ( Data(0) => Data_0, Data(1) => Data_1 );


    Or, maybe less elegent in the top level entity

    signal temp_data : std_logic_vector(1 downto 0);
    begin

    temp_data <= data_1 & data_0;

    --port map
    data => temp_data,
     
    Tricky, Nov 8, 2007
    #3
  4. =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=

    KJ Guest

    "Tricky" <> wrote in message
    news:...
    On Nov 6, 10:03 pm, Duane Clark <> wrote:
    > > Frédéric Lochon wrote:
    > >
    > > > My second idea was to map directly.
    > > > port map ( Data => Data_0 & Data_1);

    > >
    > > port map ( Data(0) => Data_0, Data(1) => Data_1 );

    >
    > Or, maybe less elegent in the top level entity
    >
    > signal temp_data : std_logic_vector(1 downto 0);
    > begin
    >
    > temp_data <= data_1 & data_0;
    >
    > --port map
    > data => temp_data,


    What you've suggested will only work if 'Data' is an input to the entity.

    A similar (but reversed) approach of defining a temporary vector would work
    if 'Data' was an output.

    No such trick that I know of will work if 'Data' is an inout...mapping each
    bit as Duane suggested will work in all situations.

    KJ
     
    KJ, Nov 8, 2007
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Chris Jones
    Replies:
    2
    Views:
    17,403
    Jim Lewis
    Jan 29, 2004
  2. GDan
    Replies:
    11
    Views:
    9,182
    violet
    Jun 29, 2006
  3. Thomas Rouam
    Replies:
    6
    Views:
    1,165
  4. THurkmans
    Replies:
    14
    Views:
    1,915
    Mike Treseler
    Aug 11, 2009
  5. KJ
    Replies:
    4
    Views:
    824
Loading...

Share This Page