Data alignment

Discussion in 'VHDL' started by Charlie84, Dec 18, 2008.

  1. Charlie84

    Charlie84

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    Hi, can u help me to imagine, how to realize this simple task?
    I have a unit A. It has two input signals - i, j. Signal i is std_logic_vector 31 downto 0. Signal j (1 downto 0) determines, how many bytes are valid on signal i in current clock. I need to align incoming bytes to complete 32 bit long word and then send it further on output (31 downto 0).
    Any advice?
     
    Charlie84, Dec 18, 2008
    #1
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  2. Charlie84

    jeppe

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    Well lets say you recieve:
    i= xx,xx,xx,b0 j=00
    i= xx,xx,b2,b1 j=01
    i= xx,xx,xx,b3 j=00

    then you should output = b3,b2,b1,b0
    ??
     
    jeppe, Dec 19, 2008
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  3. Charlie84

    Charlie84

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    exactly... on signal i can be 1,2,3 or all 4 bytes valid.. Output contains concatenated bytes aligned to complete 4-byte word. Any idea how to solve that? Some FIFO? I am using fpga.
     
    Last edited: Dec 19, 2008
    Charlie84, Dec 19, 2008
    #3
  4. Charlie84

    jeppe

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    Yes - or a statemachine - you need a clock signal for sure
     
    jeppe, Dec 19, 2008
    #4
  5. Charlie84

    jeppe

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    Try this

    It seems to work ok in simulation - but not for synthesize (too bad)

    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity BufferTest1 is
        Port ( Clk : in  STD_LOGIC;
                    I : in   STD_LOGIC_VECTOR (31 downto 0);
                    J : in   STD_LOGIC_VECTOR ( 1 downto 0);
                    o : out  STD_LOGIC_VECTOR (31 downto 0));
    end BufferTest1;

    architecture Behavioral of BufferTest1 is

    begin
        process(clk)
            variable Sh:        STD_LOGIC_VECTOR (63 downto 0) := (others=>'0');
            variable N2,N1: integer range 0 to 8 := 0;
            variable Ji:        integer range 0 to 8 := 0;
        begin
            if rising_edge(Clk) then
                Ji := conv_integer(J)+1;
                N1 := N2;
                N2 := N1+Ji;
                Sh(N2*8-1 downto N1*8) := I(Ji*8-1 downto 0);
                if N2>3 then
                    O  <= Sh(31 downto 0);
                    Sh := "00000000000000000000000000000000" & Sh(63 downto 32);
                    N2 := N2-4;
                end if;
            end if;
        end process;
    end Behavioral;
    Your welcome
    Jeppe
     
    Last edited: Dec 19, 2008
    jeppe, Dec 19, 2008
    #5
  6. Charlie84

    jeppe

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    I got some spare time - try this - not tested...

    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity BufferTest2 is
        Port ( Clk : in  STD_LOGIC;
                    I : in   STD_LOGIC_VECTOR (31 downto 0);
                    J : in   STD_LOGIC_VECTOR ( 1 downto 0);
                    o : out  STD_LOGIC_VECTOR (31 downto 0));
    end BufferTest2;

    architecture Behavioral of BufferTest2 is
        type states is (zero,one,two,three);
        signal state: states := zero;
        signal Reg: STD_LOGIC_VECTOR (23 downto 0) := (others=>'0');
    begin
        process(clk)
             variable Ji: integer range 0 to 3;
             
        begin
            if rising_edge( clk) then
            Ji := Conv_integer(J);
            case state is
                when zero =>
                    case Ji is
                        when 0 =>
                            Reg( 7 downto 0) <= I( 7 downto 0);
                            state <= One;
                        when 1 =>
                            Reg(15 downto 0) <= I(15 downto 0);
                            state <= Two;
                        when 2 =>
                            Reg(23 downto 0) <= I(23 downto 0);
                            state <= Three;
                        when 3 =>
                            O <= I;
                    end case;
                    -------------------------------------------------
                when One =>
                    case Ji is
                        when 0 =>
                            Reg( 15 downto 8) <= I( 7 downto 0);
                            state <= Two;
                        when 1 =>
                            Reg(23 downto 8) <= I(15 downto 0);
                            state <= Three;
                        when 2 =>
                            O <= I(23 downto 0)&Reg( 7 downto 0);
                            state <= Zero;
                        when 3 =>
                            O <= I(23 downto 0)&Reg( 7 downto 0);
                            Reg( 7 downto 0) <= I( 7 downto 0);
                            state <= One;
                    end case;
                    -------------------------------------------------
                when Two =>
                    case Ji is
                        when 0 =>
                            Reg( 23 downto 16) <= I( 7 downto 0);
                            state <= Three;
                        when 1 =>
                            O <= I(15 downto 0)&Reg( 15 downto 0);
                            state <= zero;
                        when 2 =>
                            O <= I(15 downto 0)&Reg( 15 downto 0);
                            Reg( 7 downto 0) <= I( 7 downto 0);
                            state <= One;
                        when 3 =>
                            O <= I(15 downto 0)&Reg( 15 downto 0);
                            Reg( 15 downto 0) <= I( 15 downto 0);
                            state <= Two;
                    end case;
                    -------------------------------------------------
                when Three =>
                    case Ji is
                        when 0 =>
                            O <= I(7 downto 0)&Reg( 23 downto 0);
                            state <= Zero;
                        when 1 =>
                            O <= I(7 downto 0)&Reg( 23 downto 0);
                            Reg( 7 downto 0) <= I( 7 downto 0);
                            state <= One;
                        when 2 =>
                            O <= I(7 downto 0)&Reg( 23 downto 0);
                            Reg( 15 downto 0) <= I( 15 downto 0);
                            state <= Two;
                        when 3 =>
                            O <= I(7 downto 0)&Reg( 23 downto 0);
                            Reg( 23 downto 0) <= I( 23 downto 0);
                            state <= Three;
                    end case;
                end case;
            end if;
        end process;

    end Behavioral;
     
    Last edited: Dec 20, 2008
    jeppe, Dec 20, 2008
    #6
  7. Charlie84

    Charlie84

    Joined:
    Dec 18, 2008
    Messages:
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    Thanks a lot.
     
    Charlie84, Dec 21, 2008
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