different variable in generate statement

[sanborne]

Hello.

I have a fairly complex for - generate loop, and I would like to
declare another variable that increments differently within the loop.
Is this possible? It would probably suffice to have two separate
generate loops, one called after the other terminates. But the second
loop would need an increment value other than 1. I'm not sure how to do
this either.

Thanks for any hints!

SY

 

[Mike Treseler]

Is this possible? It would probably suffice to have two separate
generate loops, one called after the other terminates. But the second
loop would need an increment value other than 1. I'm not sure how to do
this either.

Me neither.
I prefer declaring, initializing and updating
structured variables in a single process.
http://groups.google.com/groups/search?q=vhdl+stat_reg_t

-- Mike Treseler

 

[sanborne]

Thanks for the reply, but I don't think I follow what you are proposing
with your stat_reg_t subtype. Does this somehow help with additional
"book-keeping" variables in the for - generate loop? Or are you
proposing something else entirely?

SY

 

[Mike Treseler]

Thanks for the reply, but I don't think I follow what you are proposing
with your stat_reg_t subtype. Does this somehow help with additional
"book-keeping" variables in the for - generate loop? Or are you
proposing something else entirely?

Something completely different.
Here's an thread that shows both ways:
http://groups.google.com/groups/search?q=not_generate

Complex data structures can be handled structurally
using generate as you described,
or procedurally by declaring array or record types
and variables of those types.

Say I have an array of registered counters, that
I want to sample and restart without missing
a count. I like the clarity and conciseness
of this sort of description:

sample: if now_high(stb) then
do_all : for scan in cnt_array'range loop
-- transfer count to reg
cnt_array(scan)(2) := cnt_array(scan)(1);
-- clear count
cnt_array(scan)(1) := stat_reg_clr;
end loop do_all;
end if sample;

I could write similar procedures for initializing
and updating this counter array.

-- Mike Treseler

 

[Weng Tianxiang]

Hi,
My experiences are:
You can inbed as many loops as you want to generate any types of code.

One limitation:
All loops must be paired. Based on specifications, there is no number
of loop limitations.

For example:
A : for I in AA'range generate
B : if xxx = '1' generate
....
end generate;
end generate;
Very simple and useful. But make sure to know one exception:
A : for I in x to y generate:
....

x must be equal to or great than y as integer. Otherwise ModelSim will
generate wrong waveforms without warning.

Weng

 

[Mike Treseler]

Here's an thread that shows both ways:
http://groups.google.com/groups/search?q=not_generate

Here's another one. Generate vs. function.
http://groups.google.com/groups/search?q=vhdl+variable+function+generate+out_left

-- Mike Treseler

 

[Andy]

The use of "to" or "downto" in the generate range specification
determines whether x should be greater than or less than y. X=Y is
allowed with either to or downto. If X is greater than Y, the X to Y
should be an error in a compliant vhdl simulator/sysnthesis tool (it
should stop and issue an error during analysis/elaboration).

Andy

 

[Weng Tianxiang]

Hi Andy,
Please try ModelSim 6.0 I have been using. It doesn't generate an
error, but generates wrong waveforms that are filled with 'U' signal.

It should have generated error information, but it doesn't.

Weng