dummy projects in VHDL/Verilog

Discussion in 'VHDL' started by shumon, Sep 24, 2003.

  1. shumon

    shumon Guest

    As a person, who is does backend(post-RTL) ASIC design every
    day(synthesis,scan-jtag-bist insertion,validation and
    verification,place&route,timing analyses,DRC/LVS etc), I have lost
    touch with the world of front-end RTL coding...something that I quite
    enjoyed at school.

    Is there a web-page/resource with decent size VHDL/Verilog projects
    listed
    (I mean proper "specs") that I can use, to code for fun ? I know,
    checking out university sites for their Masters projects might be a
    good idea..but does any of you, have any other pointers ??

    Any help will be appreciated.

    -Eager to code/Shumon.
     
    shumon, Sep 24, 2003
    #1
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  2. shumon

    Jim Wu Guest

    Try www.opencores.org

    Jim Wu
    (remove capital letters)
    http://www.geocities.com/jimwu88/chips

    "shumon" <> wrote in message
    news:...
    > As a person, who is does backend(post-RTL) ASIC design every
    > day(synthesis,scan-jtag-bist insertion,validation and
    > verification,place&route,timing analyses,DRC/LVS etc), I have lost
    > touch with the world of front-end RTL coding...something that I quite
    > enjoyed at school.
    >
    > Is there a web-page/resource with decent size VHDL/Verilog projects
    > listed
    > (I mean proper "specs") that I can use, to code for fun ? I know,
    > checking out university sites for their Masters projects might be a
    > good idea..but does any of you, have any other pointers ??
    >
    > Any help will be appreciated.
    >
    > -Eager to code/Shumon.
     
    Jim Wu, Sep 24, 2003
    #2
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