E1 clock problem...

Discussion in 'VHDL' started by morppheu, Jan 11, 2010.

  1. morppheu

    morppheu

    Joined:
    Jan 11, 2010
    Messages:
    1
    Hey guys...

    I need a little help with my E1 interface.
    I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock.
    I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible?
    Today I have a process to detect if E1 F0 signals is present. If its present, I switch from internal clock to E1 clock :
    clk_res <= clk_int when E1_present = 0 else clk_e1;

    I know its a very bad design technique, but its an old code from another guy and I am looking to make the things right.
    What is the best way to interface with E1?

    Can someone help me?

    Thanks!
     
    morppheu, Jan 11, 2010
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Are clock and divided clock synchronous?

    Valentin Tihomirov, Oct 23, 2003, in forum: VHDL
    Replies:
    11
    Views:
    3,360
    louis lin
    Oct 28, 2003
  2. simon.stockton@baesystems.com
    Replies:
    4
    Views:
    752
    Peter Alfke
    Apr 27, 2006
  3. abhisheknag@gmail.com

    Arbitrary Clock Frequencies From Base Clock

    abhisheknag@gmail.com, Jun 19, 2006, in forum: VHDL
    Replies:
    5
    Views:
    2,233
    Ricardo
    Jun 23, 2006
  4. himassk
    Replies:
    1
    Views:
    1,253
    Paul Uiterlinden
    May 16, 2007
  5. pankaj.goel
    Replies:
    6
    Views:
    957
    pankaj.goel
    Nov 25, 2008
Loading...

Share This Page