Enabling clock generation

[ALuPin]

Hi,

I have a PLL in my design. This PLL generates two clocks which are
used in my design.
Now I want to cut these clocks from the design and generate my own
clocks for simulation.
The testclocks 'l_sdram_clk' and 'l_sdram_clk_90' are going to run
when the PLL is locked so that I use the 'l_pll_locked' signal to
enable the generation of the clocks.
I try that by using GENERATE. But the simulation shows that
'l_sdram_clk' and 'l_sdram_clk_90' remain undefined.

How can I solve that problem ?

I would appreciate your help.

Rgds
André


Here's the code:

architecture xy of zx is

....
signal l_pll_locked : std_logic;
-- This signal comes out of the PLL, it gets '1' in the simulation

test_1: if (l_pll_locked='1') generate
process
begin
l_sdram_clk <= '1'; wait for 3.75 ns;
l_sdram_clk <= '0'; wait for 3.75 ns;
end process;
end generate;

test_2: if (l_pll_locked='1') generate
process
begin
l_sdram_clk_90 <= '1'; wait for 1.875 ns;
l_sdram_clk_90 <= '0'; wait for 3.75 ns;
l_sdram_clk_90 <= '1'; wait for 1.875 ns;
end process;
end generate;

....
end architecture xy;

 

[Nicolas Matringe]

ALuPin a écrit:

Hi,

I have a PLL in my design. This PLL generates two clocks which are
used in my design.
Now I want to cut these clocks from the design and generate my own
clocks for simulation.
The testclocks 'l_sdram_clk' and 'l_sdram_clk_90' are going to run
when the PLL is locked so that I use the 'l_pll_locked' signal to
enable the generation of the clocks.
I try that by using GENERATE. But the simulation shows that
'l_sdram_clk' and 'l_sdram_clk_90' remain undefined.

generate allows to instantiate different components or pieces of code
depending on a generic or constant parameter. It is evaluated at
elaboration time, not during run time so you can't use it for what you
want to do.