Error during place and route: CLK0_BUFG_INST is not placed

Discussion in 'VHDL' started by lucaroccasalva@gmail.com, Mar 8, 2007.

  1. Guest

    Dear all,
    while performing a Place and Route of a reconfigurable project
    (developed following the Early Access User Guide ug208) the par return
    this error:
    ERROR: CLock Buffer "Inst_Clockman/CLK0_BUFG_INST" is not placed after
    constraint resolution. It is a requirement that all clock buffers be
    "located" during constraint resolution. PLease coorect this before
    continuing".

    In the UCF file I placed the following constraint:
    INST "Inst_Clockman" AREA_GROUP = "DCM"
    INST "Inst_Clockman/DCM_INST" LOC = "DCM_X0Y1";
    INST "Inst_Clockman/CLK0_BUFG_INST" LOC = "BUFGMUX7";
    AREA_GROUP "DCM" MODE = RECONFIG;
    AREA_GROUP "DCM" GROUP = CLOSED;

    I also tried removing the INST "Inst_Clockman/CLK0_BUFG_INST" LOC =
    "BUFGMUX7"; but the error remain the same.

    What could I do?

    Thank you very much

    Luca
    , Mar 8, 2007
    #1
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  2. Guest

    I forgot:
    I am using ISE 8.2i PR_07 with SP1.
    The device in a Spartan3 XC3S400-pq208.

    Luca
    , Mar 8, 2007
    #2
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  3. renergy

    Joined:
    Nov 14, 2007
    Messages:
    1
    I have the same problem and i'm very interested in a solution too... :hmmmm:
    renergy, Nov 14, 2007
    #3
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