error in code?

[u_stadler]

hi i have a problem with the following code i can't solve:


entity SBOX is
Port ( CLK : in std_logic;
RESET : in std_logic;
Input : in std_logic_vector(7 downto 0);
Output : out std_logic_vector(7 downto 0);
Ready : out std_logic;
Substitute : in std_logic;
Invers : in std_logic );
end SBOX;

architecture Behavioral of SBOX is

signal s_Next_Ready : std_logic;

begin

SYNC: process( CLK, RESET)
begin

if RESET = '0' then

s_Next_Ready <= '0';
Ready <= '0';
Output <= "00000000";

elsif CLK'event and CLK = '1' then

Ready <= s_Next_Ready;

end if;

end process SYNC;

SBOX: process(Input, Invers, Substitute)
begin

if Invers = '0' and Substitute = '1' then

s_Next_Ready <= '1';

elsif Substitute = '0' then

s_Next_Ready <= '0';

end if;

end process;
end Behavioral;


my testbench look like:

PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK <= transport '0';
WAIT FOR 50 ns;
CLK <= transport '1';
WAIT FOR 50 ns;

END LOOP CLOCK_LOOP;
END PROCESS;

tb : PROCESS
BEGIN
RESET <= '0';
wait for 1 us;
RESET <= '1';
wait for 100 ns;

Input <= X"02";
Invers <= '0';
Substitute <= '1';

wait;
END PROCESS;

my problem is the Ready signal. as long as Reset is '0' Ready is '0'
aswell.
if Reset goes to '1' Ready is still '0'. So far so good.
But if "Substitute" chanes to '1' Ready becomes undefines the next
positive clock egde.
any ideas?
i'm using the ise web pack.

thanks
Urban

 

[Andy Peters]

hi i have a problem with the following code i can't solve:

entity SBOX is
Port ( CLK : in std_logic;
RESET : in std_logic;
Input : in std_logic_vector(7 downto 0);
Output : out std_logic_vector(7 downto 0);
Ready : out std_logic;
Substitute : in std_logic;
Invers : in std_logic );
end SBOX;

architecture Behavioral of SBOX is

signal s_Next_Ready : std_logic;

begin
SYNC: process( CLK, RESET)
begin
if RESET = '0' then
s_Next_Ready <= '0';
Ready <= '0';
Output <= "00000000";
elsif CLK'event and CLK = '1' then
Ready <= s_Next_Ready;
end if;
end process SYNC;

SBOX: process(Input, Invers, Substitute)
begin
if Invers = '0' and Substitute = '1' then
s_Next_Ready <= '1';
elsif Substitute = '0' then
s_Next_Ready <= '0';
end if;
end process;
end Behavioral;

my testbench look like:

PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK <= transport '0';
WAIT FOR 50 ns;
CLK <= transport '1';
WAIT FOR 50 ns;

END LOOP CLOCK_LOOP;
END PROCESS;

tb : PROCESS
BEGIN
RESET <= '0';
wait for 1 us;
RESET <= '1';
wait for 100 ns;

Input <= X"02";
Invers <= '0';
Substitute <= '1';

wait;
END PROCESS;

my problem is the Ready signal. as long as Reset is '0' Ready is '0'
aswell.
if Reset goes to '1' Ready is still '0'. So far so good.
But if "Substitute" chanes to '1' Ready becomes undefines the next
positive clock egde.
any ideas?

Well, two comments.

a) the signal Input isn't used in the process SBOX, so why is it on the
sensitivity list?

b) If you synthesize, the SBOX process will create a latch. And this
process has a further issue, which is, as we will see, part of your
problem

Now, the answer: Invers and Substitute are not initialized at the start
of the simulation. Any signal dependent on them will be undefined
until you assign something to them.

I assume that you didn't bother to look at s_Next_Ready in your
simulation. If you had, you'd see that s_Next_Ready remains undefined
until either of the two conditions in the process SBOX are met. If
they're not, then you fall through without a new assignment to
s_Next_Ready, and it remains undefined.

THEN -- you're using the SYNC process to synchronize s_Next_Ready to
your clock. The async reset clears (assigns to 0) Ready. Ready
retains that value ('0') after the async reset goes away, and it will
stay at '0' until something changes it. In this case, that something
is the rising edge of CLK. At the rising edge of CLK, the process
looks at the value of s_Next_Ready and schedules that value to be
assigned to Ready. HOWEVER, since s_Next_Ready is at that point
undefined (a legal std_logic value), Ready gets assigned a Big Fat Red
'X'.

Capice?

-a

 

[Jim Lewis]

Urban,
Your simulator is correct.

The signal "s_Next_Ready" is being driven by SBOX process
and the SYNC process. You probably don't want to drive
it in the SYNC process.

A helpful visualization is to visualize each process as a
separate piece of hardware. As a result, what you have
created is two pieces of hardware whose outputs are connected
together. Generally this is not a good thing unless you
are using tristates (in general tristates are rare internal
to a chip).

Cheers,
Jim

hi i have a problem with the following code i can't solve:


entity SBOX is
Port ( CLK : in std_logic;
RESET : in std_logic;
Input : in std_logic_vector(7 downto 0);
Output : out std_logic_vector(7 downto 0);
Ready : out std_logic;
Substitute : in std_logic;
Invers : in std_logic );
end SBOX;

architecture Behavioral of SBOX is

signal s_Next_Ready : std_logic;

begin

SYNC: process( CLK, RESET)
begin

if RESET = '0' then

s_Next_Ready <= '0';
Ready <= '0';
Output <= "00000000";

elsif CLK'event and CLK = '1' then

Ready <= s_Next_Ready;

end if;

end process SYNC;

SBOX: process(Input, Invers, Substitute)
begin

if Invers = '0' and Substitute = '1' then

s_Next_Ready <= '1';

elsif Substitute = '0' then

s_Next_Ready <= '0';

end if;

end process;
end Behavioral;


my testbench look like:

PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK <= transport '0';
WAIT FOR 50 ns;
CLK <= transport '1';
WAIT FOR 50 ns;

END LOOP CLOCK_LOOP;
END PROCESS;

tb : PROCESS
BEGIN
RESET <= '0';
wait for 1 us;
RESET <= '1';
wait for 100 ns;

Input <= X"02";
Invers <= '0';
Substitute <= '1';

wait;
END PROCESS;

my problem is the Ready signal. as long as Reset is '0' Ready is '0'
aswell.
if Reset goes to '1' Ready is still '0'. So far so good.
But if "Substitute" chanes to '1' Ready becomes undefines the next
positive clock egde.
any ideas?
i'm using the ise web pack.

thanks
Urban

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[u_stadler]

Thanks for the answers!

Andy,

to a: Input is going to be used later. just forgot to remove it.

to b:
Invers and Substitute aren't initialized but it shouldn't matter as
long as RESET is low.

if i change the SBOX process to :

SBOX: process( Invers, Substitute)
begin
s_Next_Ready <= '0';

if Invers = '0' and Substitute = '1' then
s_Next_Ready <= '1';
end if;
end process;

I should cover everything?!?

but s_Next_Ready still becomes undefined after Substitute goes to '1'.
I just dont see why?

Urban

 

[u_stadler]

i just found out that only the behavioral simulation returns a strange
result.
the post place and route delivers a result as i would expect it (
s_Next_Ready goes high as soon as Substitute becomes '1' and Ready goes
high after that with the next positive clock edge)
now i totally confused

Urban

 

[Ralf Hildebrandt]

SBOX: process(Input, Invers, Substitute)
begin
if Invers = '0' and Substitute = '1' then
s_Next_Ready <= '1';
elsif Substitute = '0' then
s_Next_Ready <= '0';
end if;
end process;
end Behavioral;

Note, that this is a muxed latch!

And as Jim told you, s_Next_Ready is driven from more than one source.
To avoid such things (if they are typing errors), use
std_ulogic(_vector) - an unresolved data type. Then you get an error, if
one signal is driven from more than one process.

Use std_logic(_vector) only, if you need it (e.g. for tri-state busses).
Additionally this speeds up simulation a little bit, because no
resolution function must be computed.


Ralf