ERROR: infix expression "<=" with simple vectors

Discussion in 'VHDL' started by Trit, Feb 23, 2009.

  1. Trit

    Trit Guest

    I'm relatively inexperienced with VHDL but am doing a project
    involving it. I'm currently systematically filtering out the usual
    typos and rookie mistakes...but have a problem which I cant seem to
    fix and would like some advice.

    The problem is that the modelsim compiler doesnt seem to accept an
    assignment of signals of type std_logic_vector using quote marks of
    form <= "value"

    Example (first two errors in compile) of the relevant code

    Library IEEE;
    use IEEE.std_logic_1164.all;
    use Ieee.std_logic_unsigned.all;
    ..
    ..
    signal waitbit_state : std_logic_vector (2 downto 0);
    signal waitbit_nextstate : std_logic_vector (2 downto 0);
    ..
    ..

    30: case waitbit_state is
    31: -- wait state
    32: when "00"=>
    33: if(waitbit_start = '0') then waitbit_nextstate <= "00",
    waitbit_end <= '0';
    34: else waitbit_nextstate <= "01", waitbit_end <= '0';
    35: end if;

    error output is

    ** Error: E:/project...(33): Type error resolving infix expression
    "<=" as type ieee.std_logic_1163.std_logic_vector.
    ** Error: E:/project...(34): Type error resolving infix expression
    "<=" as type ieee.std_logic_1163.std_logic_vector.

    and a few more of the same for the other occurances in the state
    machine

    Need it be said, not being able to assign like this is awkward in a
    state machine, so does anyone know any ways to solve this? I'm
    assuming the issue is the "00" isn't being interpreted as a logic
    vector but as a numeric form?
    Trit, Feb 23, 2009
    #1
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  2. Trit

    Guest

    On Feb 23, 9:56 am, Trit <> wrote:
    > I'm relatively inexperienced with VHDL but am doing a project
    > involving it.  I'm currently systematically filtering out the usual
    > typos and rookie mistakes...but have a problem which I cant seem to
    > fix and would like some advice.
    >
    > The problem is that the modelsim compiler doesnt seem to accept an
    > assignment of signals of type std_logic_vector using quote marks of
    > form <= "value"
    >
    > Example (first two errors in compile) of the relevant code
    >
    > Library IEEE;
    > use IEEE.std_logic_1164.all;
    > use Ieee.std_logic_unsigned.all;
    > .
    > .
    > signal waitbit_state : std_logic_vector (2 downto 0);
    > signal waitbit_nextstate : std_logic_vector (2 downto 0);
    > .
    > .
    >
    > 30:     case waitbit_state is
    > 31:     -- wait state
    > 32:     when "00"=>
    > 33:             if(waitbit_start = '0') then waitbit_nextstate <= "00",
    > waitbit_end <= '0';
    > 34:             else waitbit_nextstate <= "01", waitbit_end <= '0';
    > 35:             end if;
    >
    > error output is
    >
    > ** Error: E:/project...(33): Type error resolving infix expression
    > "<=" as type ieee.std_logic_1163.std_logic_vector.
    > ** Error: E:/project...(34): Type error resolving infix expression
    > "<=" as type ieee.std_logic_1163.std_logic_vector.
    >
    > and a few more of the same for the other occurances in the state
    > machine
    >
    > Need it be said, not being able to assign like this is awkward in a
    > state machine, so does anyone know any ways to solve this?  I'm
    > assuming the issue is the "00" isn't being interpreted as a logic
    > vector but as a numeric form?


    You could try writing it like this:

    30: case waitbit_state is
    31: -- wait state
    32: when "00"=>
    33: if(waitbit_start = '0') then
    33a: waitbit_nextstate <= "00";
    33b: waitbit_end <= '0';
    34: else
    34a: waitbit_nextstate <= "01";
    34b: waitbit_end <= '0';
    35: end if;
    , Feb 23, 2009
    #2
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  3. Trit

    Guest

    On Feb 23, 10:34 am, wrote:
    > On Feb 23, 9:56 am, Trit <> wrote:
    >
    >
    >
    >
    >
    > > I'm relatively inexperienced with VHDL but am doing a project
    > > involving it.  I'm currently systematically filtering out the usual
    > > typos and rookie mistakes...but have a problem which I cant seem to
    > > fix and would like some advice.

    >
    > > The problem is that the modelsim compiler doesnt seem to accept an
    > > assignment of signals of type std_logic_vector using quote marks of
    > > form <= "value"

    >
    > > Example (first two errors in compile) of the relevant code

    >
    > > Library IEEE;
    > > use IEEE.std_logic_1164.all;
    > > use Ieee.std_logic_unsigned.all;
    > > .
    > > .
    > > signal waitbit_state : std_logic_vector (2 downto 0);
    > > signal waitbit_nextstate : std_logic_vector (2 downto 0);
    > > .
    > > .

    >
    > > 30:     case waitbit_state is
    > > 31:     -- wait state
    > > 32:     when "00"=>
    > > 33:             if(waitbit_start = '0') then waitbit_nextstate <= "00",
    > > waitbit_end <= '0';
    > > 34:             else waitbit_nextstate <= "01", waitbit_end <= '0';
    > > 35:             end if;

    >
    > > error output is

    >
    > > ** Error: E:/project...(33): Type error resolving infix expression
    > > "<=" as type ieee.std_logic_1163.std_logic_vector.
    > > ** Error: E:/project...(34): Type error resolving infix expression
    > > "<=" as type ieee.std_logic_1163.std_logic_vector.

    >
    > > and a few more of the same for the other occurances in the state
    > > machine

    >
    > > Need it be said, not being able to assign like this is awkward in a
    > > state machine, so does anyone know any ways to solve this?  I'm
    > > assuming the issue is the "00" isn't being interpreted as a logic
    > > vector but as a numeric form?

    >
    > You could try writing it like this:
    >
    > 30:     case waitbit_state is
    > 31:     -- wait state
    > 32:     when "00"=>
    > 33:             if(waitbit_start = '0') then
    > 33a:                waitbit_nextstate   <= "00";
    > 33b:                waitbit_end         <= '0';
    > 34:             else
    > 34a:               waitbit_nextstate    <= "01";
    > 34b:               waitbit_end          <= '0';
    > 35:             end if;- Hide quoted text -
    >
    > - Show quoted text -


    Whoops! Now I see the problem. The vectors are 3 bits (2 downto 0) and
    you've assigned only 2 bits ("00" and "01"). Maybe you really want
    "000" and "001".
    , Feb 23, 2009
    #3
  4. Trit

    Trit Guest

    On 23 Feb, 15:34, wrote:
    > On Feb 23, 9:56 am, Trit <> wrote:
    >
    >
    >
    >
    >
    > > I'm relatively inexperienced with VHDL but am doing a project
    > > involving it.  I'm currently systematically filtering out the usual
    > > typos and rookie mistakes...but have a problem which I cant seem to
    > > fix and would like some advice.

    >
    > > The problem is that the modelsim compiler doesnt seem to accept an
    > > assignment of signals of type std_logic_vector using quote marks of
    > > form <= "value"

    >
    > > Example (first two errors in compile) of the relevant code

    >
    > > Library IEEE;
    > > use IEEE.std_logic_1164.all;
    > > use Ieee.std_logic_unsigned.all;
    > > .
    > > .
    > > signal waitbit_state : std_logic_vector (2 downto 0);
    > > signal waitbit_nextstate : std_logic_vector (2 downto 0);
    > > .
    > > .

    >
    > > 30:     case waitbit_state is
    > > 31:     -- wait state
    > > 32:     when "00"=>
    > > 33:             if(waitbit_start = '0') then waitbit_nextstate <= "00",
    > > waitbit_end <= '0';
    > > 34:             else waitbit_nextstate <= "01", waitbit_end <= '0';
    > > 35:             end if;

    >
    > > error output is

    >
    > > ** Error: E:/project...(33): Type error resolving infix expression
    > > "<=" as type ieee.std_logic_1163.std_logic_vector.
    > > ** Error: E:/project...(34): Type error resolving infix expression
    > > "<=" as type ieee.std_logic_1163.std_logic_vector.

    >
    > > and a few more of the same for the other occurances in the state
    > > machine

    >
    > > Need it be said, not being able to assign like this is awkward in a
    > > state machine, so does anyone know any ways to solve this?  I'm
    > > assuming the issue is the "00" isn't being interpreted as a logic
    > > vector but as a numeric form?

    >
    > You could try writing it like this:
    >
    > 30:     case waitbit_state is
    > 31:     -- wait state
    > 32:     when "00"=>
    > 33:             if(waitbit_start = '0') then
    > 33a:                waitbit_nextstate   <= "00";
    > 33b:                waitbit_end         <= '0';
    > 34:             else
    > 34a:               waitbit_nextstate    <= "01";
    > 34b:               waitbit_end          <= '0';
    > 35:             end if;- Hide quoted text -
    >
    > - Show quoted text -


    I did originally try this and it didn't work (probably forgot to save
    before compiling, stare at code enough and that happens).

    Splitting the lines does seem to be working now, however, so thanks.
    It was originally separated lines but it shifted to single line when I
    changed editors. Guess I can focus on my typos now (much more fun).
    Trit, Feb 23, 2009
    #4
  5. Trit

    Trit Guest

    On 23 Feb, 15:42, wrote:
    > On Feb 23, 10:34 am, wrote:
    >
    >
    >
    >
    >
    > > On Feb 23, 9:56 am, Trit <> wrote:

    >
    > > > I'm relatively inexperienced with VHDL but am doing a project
    > > > involving it.  I'm currently systematically filtering out the usual
    > > > typos and rookie mistakes...but have a problem which I cant seem to
    > > > fix and would like some advice.

    >
    > > > The problem is that the modelsim compiler doesnt seem to accept an
    > > > assignment of signals of type std_logic_vector using quote marks of
    > > > form <= "value"

    >
    > > > Example (first two errors in compile) of the relevant code

    >
    > > > Library IEEE;
    > > > use IEEE.std_logic_1164.all;
    > > > use Ieee.std_logic_unsigned.all;
    > > > .
    > > > .
    > > > signal waitbit_state : std_logic_vector (2 downto 0);
    > > > signal waitbit_nextstate : std_logic_vector (2 downto 0);
    > > > .
    > > > .

    >
    > > > 30:     case waitbit_state is
    > > > 31:     -- wait state
    > > > 32:     when "00"=>
    > > > 33:             if(waitbit_start = '0') then waitbit_nextstate <= "00",
    > > > waitbit_end <= '0';
    > > > 34:             else waitbit_nextstate <= "01", waitbit_end <= '0';
    > > > 35:             end if;

    >
    > > > error output is

    >
    > > > ** Error: E:/project...(33): Type error resolving infix expression
    > > > "<=" as type ieee.std_logic_1163.std_logic_vector.
    > > > ** Error: E:/project...(34): Type error resolving infix expression
    > > > "<=" as type ieee.std_logic_1163.std_logic_vector.

    >
    > > > and a few more of the same for the other occurances in the state
    > > > machine

    >
    > > > Need it be said, not being able to assign like this is awkward in a
    > > > state machine, so does anyone know any ways to solve this?  I'm
    > > > assuming the issue is the "00" isn't being interpreted as a logic
    > > > vector but as a numeric form?

    >
    > > You could try writing it like this:

    >
    > > 30:     case waitbit_state is
    > > 31:     -- wait state
    > > 32:     when "00"=>
    > > 33:             if(waitbit_start = '0') then
    > > 33a:                waitbit_nextstate   <= "00";
    > > 33b:                waitbit_end         <= '0';
    > > 34:             else
    > > 34a:               waitbit_nextstate    <= "01";
    > > 34b:               waitbit_end          <= '0';
    > > 35:             end if;- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Whoops! Now I see the problem. The vectors are 3 bits (2 downto 0) and
    > you've assigned only 2 bits ("00" and "01"). Maybe you really want
    > "000" and "001".- Hide quoted text -
    >
    > - Show quoted text -


    yeah, that problem I corrected earlier. Bad day = disorganised heap
    of files in various states of debugging. I've just spent 5 mins
    putting them in order so I can be more systematic lol. I'll make sure
    the version i end up with has that one fixed, (it's a pretty
    distictive error anyway). Mostly I have to worry about else if ->
    elsif and missing underscores in signal names. Sorry about that
    confusion.
    Trit, Feb 23, 2009
    #5
  6. Trit

    Tricky Guest

    May I recommend, as you are new to VHDL, that you stop using
    std_logic_unsigned/arith/signed and instead use the package
    ieee.numeric_std instead? (As it is an IEEE standard, the others are
    not).
    Getting into the habit now will save you grief on here later.
    Tricky, Feb 23, 2009
    #6
  7. Trit

    Trit Guest

    On 23 Feb, 16:17, Tricky <> wrote:
    > May I recommend, as you are new to VHDL, that you stop using
    > std_logic_unsigned/arith/signed and instead use the package
    > ieee.numeric_std instead?  (As it is an IEEE standard, the others are
    > not).
    > Getting into the habit now will save you grief on here later.


    Yeah, 99% of the time I don't need it and dont include it (especially
    since I've seen the grief others have, and especially since the
    libraries are defined per entity). There are just a few cases such as
    counters where I need to add 1 and need the unsigned library, unless
    there is a way to do a increment without it?
    Trit, Feb 23, 2009
    #7
  8. Trit

    Andy Peters Guest

    On Feb 23, 9:58 am, Trit <> wrote:
    > On 23 Feb, 16:17, Tricky <> wrote:
    >
    > > May I recommend, as you are new to VHDL, that you stop using
    > > std_logic_unsigned/arith/signed and instead use the package
    > > ieee.numeric_std instead?  (As it is an IEEE standard, the others are
    > > not).
    > > Getting into the habit now will save you grief on here later.

    >
    > Yeah, 99% of the time I don't need it and dont include it (especially
    > since I've seen the grief others have, and especially since the
    > libraries are defined per entity).  There are just a few cases such as
    > counters where I need to add 1 and need the unsigned library, unless
    > there is a way to do a increment without it?


    Use numeric_std instead.

    -a
    Andy Peters, Feb 23, 2009
    #8
  9. Trit

    Trit Guest

    On 23 Feb, 18:17, Andy Peters <> wrote:
    > On Feb 23, 9:58 am, Trit <> wrote:
    >
    > > On 23 Feb, 16:17, Tricky <> wrote:

    >
    > > > May I recommend, as you are new to VHDL, that you stop using
    > > > std_logic_unsigned/arith/signed and instead use the package
    > > > ieee.numeric_std instead?  (As it is an IEEE standard, the others are
    > > > not).
    > > > Getting into the habit now will save you grief on here later.

    >
    > > Yeah, 99% of the time I don't need it and dont include it (especially
    > > since I've seen the grief others have, and especially since the
    > > libraries are defined per entity).  There are just a few cases such as
    > > counters where I need to add 1 and need the unsigned library, unless
    > > there is a way to do a increment without it?

    >
    > Use numeric_std instead.
    >
    > -a


    that will still allow simple assignment of type x <= x + '1'; ?
    convenient. I'll do that thanks

    Cheers for the help all, finally managed to turn today around into a
    productive session (after an appallingly disappointing weekend of
    downloading useless applications) thanks to your advice
    Trit, Feb 23, 2009
    #9
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