ERROR MESSAGE IN MODELSIM

Discussion in 'VHDL' started by Amit, Jun 9, 2007.

  1. Amit

    Amit Guest

    HELLO GROUP,

    IN THE FOLLOWING BLOCK. I'M GETTING ERROR AS:
    ** Error: arbit.vhd(39): Case statement covers only 1 out of 5 cases.
    <<<<< ERROR
    ** Error: arbit.vhd(18): Nonresolved signal 'state_reg' has multiple
    sources. <<<< ERROR



    architecture arbiter_discipline_arch of Arbiter is

    type arbit_state_type is (init, grant0, grant1, grant2, grant3);
    signal state_reg, state_next : arbit_state_type; <<<<<<<<<<<<<<<<<<
    LINE 18

    begin

    --state register
    process(clock, reset)
    begin

    if (reset = '1') then
    state_reg <= init;
    elsif(clock'event and clock = '1' ) then
    state_reg <= state_next;
    end if;

    end process;

    process(state_reg, acknowledge, request)
    begin

    acknowledge <= "0000";

    case state_reg is <<<<<<<<<<<<<<<<<< LINE 39

    when init =>
    if request(0) = '1' then
    state_reg <= grant0;
    else
    state_reg <= init;
    end if;


    end case;
    end process;

    THANKS,
     
    Amit, Jun 9, 2007
    #1
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  2. Amit

    Amit Guest

    On Jun 8, 4:36 pm, Amit <> wrote:
    > HELLO GROUP,
    >
    > IN THE FOLLOWING BLOCK. I'M GETTING ERROR AS:
    > ** Error: arbit.vhd(39): Case statement covers only 1 out of 5 cases.
    > <<<<< ERROR
    > ** Error: arbit.vhd(18): Nonresolved signal 'state_reg' has multiple
    > sources. <<<< ERROR
    >
    > architecture arbiter_discipline_arch of Arbiter is
    >
    > type arbit_state_type is (init, grant0, grant1, grant2, grant3);
    > signal state_reg, state_next : arbit_state_type; <<<<<<<<<<<<<<<<<<
    > LINE 18
    >
    > begin
    >
    > --state register
    > process(clock, reset)
    > begin
    >
    > if (reset = '1') then
    > state_reg <= init;
    > elsif(clock'event and clock = '1' ) then
    > state_reg <= state_next;
    > end if;
    >
    > end process;
    >
    > process(state_reg, acknowledge, request)
    > begin
    >
    > acknowledge <= "0000";
    >
    > case state_reg is <<<<<<<<<<<<<<<<<< LINE 39
    >
    > when init =>
    > if request(0) = '1' then
    > state_reg <= grant0;
    > else
    > state_reg <= init;
    > end if;
    >
    > end case;
    > end process;
    >
    > THANKS,




    solved. thanks anyway.
     
    Amit, Jun 9, 2007
    #2
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