Error message

Discussion in 'VHDL' started by Marcus, Nov 14, 2004.

  1. Marcus

    Marcus Guest

    I am new to VHDL and already have a problem. I get a error message and
    it dont have an idea what I am doing wrong. I want to use 2 processes
    and probably some more later. When the first process updates the
    counter I want to do something in the second process. The lines I have
    in the second process are just for testing and will be changed later.

    I get the following error message when I translate the code.
    Synsthesis is ok.

    ERROR:NgdBuild:605 - logical root block 'generator' with type
    'generator' is unexpanded. Symbol 'generator' is not supported in
    target 'xpla3'.

    CODE:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    -- Uncomment the following lines to use the declarations that are
    -- provided for instantiating Xilinx primitive components.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity generator is
    Port ( reset : in std_logic;
    clock : in std_logic;
    data : out std_logic;
    run : in std_logic;
    mode : in std_logic_vector(1 downto 0));
    end entity generator;

    architecture Behavioral of generator is
    signal counter :std_logic_vector(5 downto 0);
    signal header_c :std_logic_vector(3 downto 0);
    signal data_c :std_logic_vector(4 downto 0);
    signal checksum_c :std_logic_vector(3 downto 0);
    signal running :std_logic;
    begin

    clock_count: process (clock, reset)
    begin
    if reset = '1' then
    counter <= "000000";
    header_c <="0000";
    running <= '0';
    data_c <= "00000";
    checksum_c <= "0000";
    elsif rising_edge(clock) then
    counter <= counter + 1;
    end if ;
    end process clock_count;

    start : process (counter)
    begin
    if counter = "100011" then
    counter <= "000000";
    else
    counter <= counter + 1;
    end if;
    end process start;
    end Behavioral;
     
    Marcus, Nov 14, 2004
    #1
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  2. Marcus wrote:
    > I am new to VHDL and already have a problem. I get a error message and
    > it dont have an idea what I am doing wrong.


    Everybody shorts process outputs together the first time out.
    You are driving the "counter" port from more than one process.
    Merge the reset clause into your second process, then delete
    the first process.

    -- Mike Treseler
     
    Mike Treseler, Nov 14, 2004
    #2
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