Feedback mux created for signal data

Discussion in 'VHDL' started by valentin tihomirov, Aug 31, 2004.

  1. Sinplify shows the following warnings

    Feedback mux created for signal data[1:0]. Did you forget the set/reset
    assignment for this signal?
    Feedback mux created for signal data[3:0]. Did you forget the set/reset
    assignment for this signal?
    Feedback mux created for signal data[4:0]. Did you forget the set/reset
    assignment for this signal?
    Feedback mux created for signal data[7:0]. Did you forget the set/reset
    assignment for this signal?



    on this code:


    architecture RTL of SHIFT_REGISTER is
    signal DATA: STD_LOGIC_VECTOR(SIZE-1 downto 0);
    begin
    REG: process (CLK, RESET)
    variable BitCnt: Integer range 0 to 8;
    begin
    if RESET = '1' then -- WARNINGS on this line
    null;
    DATA <= (others => '-');
    elsif Rising_Edge(CLK) then
    if ENABLE = '1' then
    if LOAD = '1' then

    -- VHDL not working for SIZE=1
    -- DATA <= SIN & DATA (SIZE - 1 downto 1);

    if SIZE = 1 then
    DATA(0) <= SIN;
    else
    DATA <= SIN & DATA (SIZE - 1 downto 1);
    end if;

    end if;
    end if;
    end if;
    end process REG;

    POUT <= DATA;

    end RTL;
     
    valentin tihomirov, Aug 31, 2004
    #1
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  2. valentin tihomirov

    trican Guest

    trican, Aug 31, 2004
    #2
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  3. "valentin tihomirov" <> wrote

    > if RESET = '1' then -- WARNINGS on this line
    > null;
    > DATA <= (others => '-');


    Why do you use the null statement?

    It seems that your synthesis tool didn't come along with reset to
    don't-care. So use a dedicated set or reset. I bet your results will
    be fine than.

    bye Thomas
     
    Thomas Stanka, Sep 1, 2004
    #3
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