FF array, is it a valid way to write it?

Discussion in 'VHDL' started by MM, Jun 18, 2004.

  1. MM

    MM Guest

    Hi all,

    Is the code below valid (including for synthesis)?


    signal clk : std_logic_vector(0 to 3);

    PROC:
    process (clk)
    begin
    LP1:
    for i in 0 to NUM loop
    if clk(i)'event and clk(i)='0' then
    queue(i) <= ldata(i);
    end if;
    end loop;
    end process;

    Thanks,
    /Mikhail
    MM, Jun 18, 2004
    #1
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  2. MM

    JJ Guest

    No.

    You need to create a component model for the ff and then use a for-generate
    statement loop that instantiates and connects them together.



    "MM" <> wrote in message
    news:...
    > Hi all,
    >
    > Is the code below valid (including for synthesis)?
    >
    >
    > signal clk : std_logic_vector(0 to 3);
    >
    > PROC:
    > process (clk)
    > begin
    > LP1:
    > for i in 0 to NUM loop
    > if clk(i)'event and clk(i)='0' then
    > queue(i) <= ldata(i);
    > end if;
    > end loop;
    > end process;
    >
    > Thanks,
    > /Mikhail
    >
    >
    JJ, Jun 19, 2004
    #2
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  3. JJ wrote:

    > You need to create a component model for the ff and then use a for-generate
    > statement loop that instantiates and connects them together.


    Could anybody tell me, why:


    signal clk : std_logic_vector(0 to 3);

    gen_gueues : for i in 0 to NUM generate
    process (clk)
    begin
    if clk(i)'event and clk(i)='0' then
    queue(i) <= ldata(i);
    end if;
    end process;
    end generate;


    is not allowed? This works in Cadence Leapfrog for simulation, but
    Synopys Design Analyzer gives an error during synthesis.


    Ralf
    Ralf Hildebrandt, Jun 19, 2004
    #3
  4. Ralf Hildebrandt <> writes:

    > JJ wrote:
    >
    >> You need to create a component model for the ff and then use a for-generate
    >> statement loop that instantiates and connects them together.

    >
    > Could anybody tell me, why:
    >
    >
    > signal clk : std_logic_vector(0 to 3);
    >
    > gen_gueues : for i in 0 to NUM generate
    > process (clk)
    > begin
    > if clk(i)'event and clk(i)='0' then
    > queue(i) <= ldata(i);
    > end if;
    > end process;
    > end generate;
    >
    > is not allowed? This works in Cadence Leapfrog for simulation, but
    > Synopys Design Analyzer gives an error during synthesis.


    I guess that Synopsys's Design Compiler don't like the idea of
    generating processes. DC is well known to be quite limited in it's
    support of VHDL constructs, e.g. only generics of integer type is
    allowed, even though naturals should make no difference.

    They're coming out with a new frontend based on Presto, but it's still
    beta. We got the beta to break in spectacular ways, e.g. replacing an
    "i" with a "j" could get a for-loop to work. At that point, we
    realized the new frontend wasn't ready for prime time (no [tool] pun
    intended).


    /Kai
    Kai Harrekilde-Petersen, Jun 19, 2004
    #4
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