GENERATE - cascaded

Discussion in 'VHDL' started by ALuPin@web.de, Apr 28, 2008.

  1. Guest

    Hi,

    I have the following GENERATE structure:


    u_cluster : for m in cCLUSTER downto 0 generate

    i_inst : xy
    port map ( xyz_i => ...);

    end generate;


    Now I want to do the following:

    u_cluster : for m in cCLUSTER downto 0 generate

    u_cases: if m=0 or m=2 generate --else : no instantiation
    i_inst : xy
    port map ( xyz_i => ...);

    end generate;

    end generate;

    How do I build that structure correctly ? Thank you for your
    suggestions.

    Rgds,
    Andre
     
    , Apr 28, 2008
    #1
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  2. KJ Guest

    On Apr 28, 5:27 am, "" <> wrote:
    > Hi,
    >
    > I have the following GENERATE structure:
    >
    > u_cluster : for m in cCLUSTER downto 0 generate
    >
    > i_inst : xy
    > port map ( xyz_i => ...);
    >
    > end generate;
    >
    > Now I want to do the following:
    >
    > u_cluster : for m in cCLUSTER downto 0 generate
    >
    > u_cases: if m=0 or m=2 generate     --else : no instantiation
    > i_inst : xy
    > port map ( xyz_i => ...);
    >
    > end generate;
    >
    > end generate;
    >
    > How do I build that structure correctly ? Thank you for your
    > suggestions.
    >
    > Rgds,
    > Andre


    What you have shown is correct...try it and see.

    KJ
     
    KJ, Apr 28, 2008
    #2
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  3. Guest

    Hi KJ,

    yes you are right. I was facing problems with some projekt files
    making trouble to the compiler.
    It works fine now.

    Thank you.

    Rgds,
    Andre
     
    , Apr 28, 2008
    #3
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