generic

Discussion in 'VHDL' started by Brian, Nov 6, 2009.

  1. Brian

    Brian Guest

    I am tying to create a module with a generic, but something is not
    correct. Please help. How do I do this correctly?

    entity downsample_by_two is
    generic (
    wordlength : integer := 14;
    ce_clk48_polarity : std_logic := '1' -- 1: hi, 0: lo
    );
    port(
    -- INPUT PORTS --
    x : in std_logic_vector(wordlength-1 downto 0);
    ce_clk48 : in std_logic;
    -- OUTPUT PORTS --
    7 : out std_logic_vector(wordlength-1 downto 0)
    );
    end entity;


    then on down in the code I want to use


    if ce_clk48 = ce_clk48_polarity then
    Brian, Nov 6, 2009
    #1
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  2. Brian

    Andy Guest

    On Nov 6, 6:58 am, Brian <> wrote:
    > I am tying to create a module with a generic, but something is not
    > correct. Please help. How do I do this correctly?
    >
    > entity downsample_by_two is
    >         generic (
    >                 wordlength              : integer       := 14;
    >                 ce_clk48_polarity       : std_logic := '1' -- 1: hi, 0: lo
    >                 );
    >         port(
    >                 -- INPUT PORTS --
    >                 x               : in std_logic_vector(wordlength-1 downto 0);
    >                 ce_clk48        : in std_logic;
    >                 -- OUTPUT PORTS --
    >                 7               : out std_logic_vector(wordlength-1 downto 0)
    >                 );
    > end entity;
    >
    > then on down in the code I want to use
    >
    > if ce_clk48 = ce_clk48_polarity then


    Your output port name is not a legal identifier in VHDL.

    Andy
    Andy, Nov 6, 2009
    #2
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