generic

[Brian]

I am tying to create a module with a generic, but something is not
correct. Please help. How do I do this correctly?

entity downsample_by_two is
generic (
wordlength : integer := 14;
ce_clk48_polarity : std_logic := '1' -- 1: hi, 0: lo
);
port(
-- INPUT PORTS --
x : in std_logic_vector(wordlength-1 downto 0);
ce_clk48 : in std_logic;
-- OUTPUT PORTS --
7 : out std_logic_vector(wordlength-1 downto 0)
);
end entity;


then on down in the code I want to use


if ce_clk48 = ce_clk48_polarity then

 

[Andy]

I am tying to create a module with a generic, but something is not
correct. Please help. How do I do this correctly?

entity downsample_by_two is
        generic (
                wordlength              : integer       := 14;
                ce_clk48_polarity       : std_logic := '1' -- 1: hi, 0: lo
                );
        port(
                -- INPUT PORTS --
                x               : in std_logic_vector(wordlength-1 downto 0);
                ce_clk48        : in std_logic;
                -- OUTPUT PORTS --
                7               : out std_logic_vector(wordlength-1 downto 0)
                );
end entity;

then on down in the code I want to use

if ce_clk48 = ce_clk48_polarity then

Your output port name is not a legal identifier in VHDL.

Andy