Help>Multiplier Code > State Machine Style > VHDL

Discussion in 'VHDL' started by kameshwar_kaushik, Jan 26, 2006.

  1. kameshwar_kaushik

    kameshwar_kaushik

    Joined:
    Jan 26, 2006
    Messages:
    6
    here is my code
    /***************************************************/
    Library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_signed.all;
    use IEEE.numeric_std.all;

    entity multiplier is
    port (A: in std_logic_vector(3 downto 0);
    B: in std_logic_vector(3 downto 0);
    Rst: in std_logic;
    Clk: in std_logic;
    O: out std_logic_vector(7 downto 0));
    end multiplier;

    architecture multiplier of multiplier is
    signal prod: std_logic_vector(7 downto 0);
    signal temp: std_logic_vector(8 downto 0);
    signal count: std_logic_vector (3 downto 0);
    signal case_temp: std_logic_vector(1 downto 0);
    signal carry: std_logic;
    signal current_state,next_state: std_logic_vector(3 downto 0);
    begin
    process (Rst,Clk)
    begin
    if(Rst ='1') then
    current_state<=(others => '0');
    else
    if(Clk='1') then
    current_state<=next_state;
    end if;
    end if;
    end process;

    process(Clk)
    begin
    if(Clk'event and Clk='1' and Rst='0') then
    case current_state is
    when "0000" =>
    prod<= "0000" & A;
    carry<= '0';
    temp<= (others => '0');
    count <= (others => '0');
    case_temp<= (others => '0');
    next_state<= "0001";
    when "0001" =>
    case_temp <= prod(0) & carry;
    case (case_temp) is
    when "00" => next_state<= "0100";
    when "01" => next_state<= "0010";
    when "10" => next_state<= "0011";
    when "11" => next_state<= "0100";
    when others=> next_state<= "0000";
    end case;
    count<=count +'1';
    when "0010" =>
    prod(7 downto 4) <= prod(7 downto 4) + B;
    next_state<= "0100";
    when "0011" =>
    prod(7 downto 4) <= prod(7 downto 4) + not(B) +'1';
    next_state<= "0100";
    when "0100" =>
    temp <= prod(7) & prod(7 downto 0);
    prod <= temp(8 downto 1);
    carry <= temp(0);
    next_state<= "0101";
    when "0101" =>
    if (not(count = "0100")) then
    next_state<="0001";
    else
    next_state<="0110";
    end if;
    when "0110" => O<= prod;
    when others => null;
    end case;
    end if;
    end process;

    end architecture;

    /****************************************************/

    this is my code based on booths algorithm for fixed point multiplication (4 bit x 4-bit).

    The code compiles fine...but the problem is with the execution.

    I track the progress of the multiplier block using "count" variable. The next_state and current_state variables define which state the block is in and which state it is going to be in.

    There are 2 process blocks' . 1 is combinational and 1 is sequential.

    but the state transistion is not happening correctly because the process block values are not being updated correctly at the end of every process block. Infact, the trace shows that every state is executed twice . This is not how it should be. Can anyone tell me why?

    // PS: The same code works well in verilog, i've tried it in verilog
     
    kameshwar_kaushik, Jan 26, 2006
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Markus Fuchs

    4527 (bcd rate multiplier) vhdl code

    Markus Fuchs, Sep 17, 2003, in forum: VHDL
    Replies:
    0
    Views:
    1,293
    Markus Fuchs
    Sep 17, 2003
  2. Viswan
    Replies:
    9
    Views:
    12,167
    Ray Andraka
    Feb 11, 2004
  3. chi_rulez

    VHDL code for multiplier

    chi_rulez, Aug 21, 2004, in forum: VHDL
    Replies:
    7
    Views:
    20,732
    VHDLCoder
    Oct 17, 2011
  4. sheeja
    Replies:
    2
    Views:
    855
    Ray Andraka
    Mar 15, 2007
  5. jaipalreddy
    Replies:
    0
    Views:
    3,614
    jaipalreddy
    Apr 14, 2007
Loading...

Share This Page