Help with VHDL

[Centurion210]

Hello everyone

Well i'm kinda stuck in a project where i need to use out logic pins to do internal logic in my project... i've been reading several books/manuals and they all said i'd have to use buffer as port type to do this, so i'll attach my .vhd project in here:

-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM		"Quartus II"
-- VERSION		"Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition"
-- CREATED ON		"Thu Nov 25 16:47:32 2010"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY maquina IS 
	PORT
	(
		moeda5 :  IN  STD_LOGIC;
		moeda10 :  IN  STD_LOGIC;
		moeda25 :  IN  STD_LOGIC;
		moeda50 :  IN  STD_LOGIC;
		moeda100 :  IN  STD_LOGIC;
		clock :  IN  STD_LOGIC;
		clear :  IN  STD_LOGIC;
		precoproduto :  IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
		precoigual :  OUT  STD_LOGIC;
		recebidomaior :  buffer  STD_LOGIC;
		produtomaior :  out  STD_LOGIC;
		troco :  buffer  STD_LOGIC_VECTOR(4 DOWNTO 0);
		d5 : out std_logic
		--dispensa5, dispensa10, dispensa25, dispensa50, dispensa100 : out std_logic
	);
END maquina;

ARCHITECTURE bdf_type OF maquina IS

ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;

COMPONENT mult2
	PORT(dataa : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;

ATTRIBUTE black_box OF mult2: COMPONENT IS true;
ATTRIBUTE noopt OF mult2: COMPONENT IS true;

COMPONENT contadormoeda5
	PORT(sclr : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 clk_en : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
	);
END COMPONENT;

COMPONENT contadormoeda10
	PORT(sclr : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 clk_en : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
	);
END COMPONENT;

COMPONENT comparadorvalorproduto_valorrecebido
	PORT(dataa : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		 datab : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		 aeb : OUT STD_LOGIC;
		 agb : OUT STD_LOGIC;
		 alb : OUT STD_LOGIC
	);
END COMPONENT;

COMPONENT calculadoratroco
	PORT(dataa : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		 datab : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		 result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
	);
END COMPONENT;

COMPONENT contadormoeda25
	PORT(sclr : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 clk_en : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END COMPONENT;

COMPONENT contadormoeda50
	PORT(sclr : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 clk_en : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END COMPONENT;

COMPONENT contadormoeda100
	PORT(sclr : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 clk_en : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
	);
END COMPONENT;

COMPONENT mult5
	PORT(dataa : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		 result : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
	);
END COMPONENT;

COMPONENT mult10
	PORT(dataa : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;

COMPONENT mult20
	PORT(dataa : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;

COMPONENT somadinheiro
	PORT(data0x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
		 data1x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
		 data2x : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		 data3x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
		 data4x : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		 result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
	);
END COMPONENT;

SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC_VECTOR(4 DOWNTO 0);
[B]signal dispensa5 : std_logic;[/B]


BEGIN 

[B]dispensa5 <= '1' after 1ns, '0' after 11ns when recebidomaior = '1' and troco = "00001";
d5 <= dispensa5;[/B]

b2v_inst : contadormoeda5
PORT MAP(sclr => clear,
		 clock => clock,
		 clk_en => moeda5,
		 q => SYNTHESIZED_WIRE_10);


b2v_inst1 : contadormoeda10
PORT MAP(sclr => clear,
		 clock => clock,
		 clk_en => moeda10,
		 q => SYNTHESIZED_WIRE_2);


b2v_inst16 : comparadorvalorproduto_valorrecebido
PORT MAP(dataa => SYNTHESIZED_WIRE_11,
		 datab => precoproduto,
		 aeb => precoigual,
		 agb => recebidomaior,
		 alb => produtomaior);


b2v_inst19 : calculadoratroco
PORT MAP(dataa => SYNTHESIZED_WIRE_11,
		 datab => precoproduto,
		 result => troco);


b2v_inst2 : contadormoeda25
PORT MAP(sclr => clear,
		 clock => clock,
		 clk_en => moeda25,
		 q => SYNTHESIZED_WIRE_3);


b2v_inst3 : contadormoeda50
PORT MAP(sclr => clear,
		 clock => clock,
		 clk_en => moeda50,
		 q => SYNTHESIZED_WIRE_4);


b2v_inst4 : contadormoeda100
PORT MAP(sclr => clear,
		 clock => clock,
		 clk_en => moeda100,
		 q => SYNTHESIZED_WIRE_5);


b2v_inst5 : mult2
PORT MAP(dataa => SYNTHESIZED_WIRE_2,
		 result => SYNTHESIZED_WIRE_9);


b2v_inst6 : mult5
PORT MAP(dataa => SYNTHESIZED_WIRE_3,
		 result => SYNTHESIZED_WIRE_8);


b2v_inst7 : mult10
PORT MAP(dataa => SYNTHESIZED_WIRE_4,
		 result => SYNTHESIZED_WIRE_7);


b2v_inst8 : mult20
PORT MAP(dataa => SYNTHESIZED_WIRE_5,
		 result => SYNTHESIZED_WIRE_6);


b2v_inst9 : somadinheiro
PORT MAP(data0x => SYNTHESIZED_WIRE_6,
		 data1x => SYNTHESIZED_WIRE_7,
		 data2x => SYNTHESIZED_WIRE_8,
		 data3x => SYNTHESIZED_WIRE_9,
		 data4x => SYNTHESIZED_WIRE_10,
		 result => SYNTHESIZED_WIRE_11);

END bdf_type;

*Bold parts are the one i'm talking about in this post. Well, that code compiles normally, but when i try to simulate it with waveforms, it just put "dispensa5" signal in high level all the time. Seems its overlapping the logic and puttin '1' on the signal directly. I've tried everything, if's, processess, cases, well... i'm starting to desperate!

can someone enlight me ?

thanks in advance!