How did Ashenden know about STD_INPUT?

Discussion in 'VHDL' started by valtih1978, Sep 16, 2013.

  1. valtih1978

    valtih1978 Guest

    I see that VHDL2008 provides std.textio package, which defines file
    INPUT: TEXT open READ_MODE is "STD_INPUT". But, this is the only one
    occurence of STD_INPUT in the whole document. So, nowhere 2008 specifies
    that files named STD_INPUT must be mapped to something special. Why do
    Ashenden and modelsim do that?
    valtih1978, Sep 16, 2013
    #1
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  2. valtih1978

    Jim Lewis Guest

    Being defined concisely in one place (std.textio) is sufficient!

    ....

    So if you really like brain teasers, where in the standard does it say the following parentheses are required:

    Y <= (A and B) or C ;
    Jim Lewis, Sep 16, 2013
    #2
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  3. valtih1978

    Dio Gratia Guest

    On Tuesday, September 17, 2013 6:19:04 AM UTC+12, Jim Lewis wrote:
    >
    > So if you really like brain teasers, where in the standard does it say the following parentheses are required:
    >
    >
    >
    > Y <= (A and B) or C ;


    9.1 General
    ...
    expression ::=
    relation { and relation }
    | relation { or relation }
    | relation { xor relation }
    | relation [ nand relation ]
    | relation [ nor relation ]
    | relation { xnor relation }

    relation ::=
    shift_expression [ relational_operator shift_expression ]

    shift_expression ::=
    simple_expression [ shift_operator simple_expression ]

    simple_expression ::=
    [ sign ] term { adding_operator term }

    term ::=
    factor { multiplying_operator factor }

    factor ::=
    primary [ ** primary ]
    | abs primary
    | not primary

    primary ::=
    name
    | literal
    | aggregate
    | function_call
    | qualified_expression
    | type_conversion
    | allocator
    | ( expression ) <== RIGHT HERE
    Dio Gratia, Sep 18, 2013
    #3
  4. valtih1978

    valtih1978 Guest

    +1
    valtih1978, Sep 18, 2013
    #4
  5. valtih1978

    Andy Guest

    On Wednesday, September 18, 2013 5:08:08 AM UTC-5, Dio Gratia wrote:
    > | ( expression ) <== RIGHT HERE


    Not exactly... Jim asked where the standard REQUIRES the parentheses in his example.

    If that chain of definitions actually REQUIRED parentheses in his example, then they would also be required in the following example, in which they are not required:

    Y <= A and B and C;

    So either that chain can be interpreted to allow, but not require, parentheses around every pair of operands with a logic operator, or it is incorrectly stated.

    The intent of that chain was to define operator precedence, and to establish that logical operators do not have a defined precedence over each other.

    Andy
    Andy, Sep 18, 2013
    #5
  6. valtih1978

    valtih1978 Guest

    At first, my example of "not specified" is more correct than Jim's
    because meaning of parenthis is discussed in the operator precedence:
    "parentheses can be used to control the association of operators and
    operands." (9.2.1 Operators General). Secondly, if you insist that there
    is no requirement in (A or B) or C then there is no requirement for
    STD_INPUT to be mapped to console or whatever. Please do not
    overcomplicate matters with useless examples.
    valtih1978, Sep 18, 2013
    #6
  7. valtih1978

    Dio Gratia Guest

    On Thursday, September 19, 2013 5:11:55 AM UTC+12, Andy wrote:
    > On Wednesday, September 18, 2013 5:08:08 AM UTC-5, Dio Gratia wrote:
    >
    > > | ( expression ) <== RIGHT HERE

    >
    >
    >
    > Not exactly... Jim asked where the standard REQUIRES the parentheses in his example.
    >
    > If that chain of definitions actually REQUIRED parentheses in his example, then they would also be required in the following example, in which they are not required:
    >
    >
    > Y <= A and B and C;
    >


    > So either that chain can be interpreted to allow, but not require, parentheses around every pair of operands with a logic operator, or it is incorrectly stated.
    >
    > The intent of that chain was to define operator precedence, and to establish that logical operators do not have a defined precedence over each other..
    >


    (Clause references are from IEEE Std 1076-2008)

    The right hand side first production for expression allows A and B and C to be in the same expression, not requiring parenthesis.

    { and relation }

    1.3.2 Syntactic description

    "f) Braces { } enclose a repeated item or items on the right-hand side of aproduction. The items may appear zero or more times; the repetitions occurfrom left to right as with an equivalent left-recursive rule."

    You'll also note from the BNF that nand and nor require single instances inan expression, (also from 1.3.2):

    "c) Square brackets [ ] enclose optional items on the right-hand side of a production;"

    with no provision for repetition, because nand and nor aren't associative. The BNF found in Clause 9. Expressions is normative. The point is to insure parenthesis are used where the are required.

    And yes, I'm aware that Jim's signal assignment statement is capable of producing the right answer without parenthesis due to occurrence left to rightin a left recursion production if it weren't forced to be comprised of twoexpressions in a left recursion.

    Note

    Y <= (A and B and C) or D;

    is 'legal' while

    Y <= A and B and C or D;

    isn't, according to the BNF.

    While I don't have access to a lot of different VHDL analyzers currently, there are those that devolve expressions according to the BNF from 9.1, or say 7.1 Expressions, from 1076-1993 as in the case of ghdl with it's awkwarderror message for Jim's signal assignment:

    only one type of logical operators may be used to combine relation

    I'd think operators should be singular while relation should be pluralized.

    ghdl also 'correctly' requires single occurrences of nand and nor with parse error messages:

    sequence of 'nor' or 'nand' not allowed

    and

    ('nor' and 'nand' are not associative)

    There's a subtle message here, that the BNF found in the standard other than in an appendix is normative. And try as you might there doesn't appear to be another place in the standard that requires the parenthesis.

    You can look in non-authoritative texts such as Mentor Graphics VHDL Reference Manual from 1994, which tells you somewhere between pages 2-3 and 2-9 (PDF pages 47-53) that the parenthesis are required in discussing expressions.

    My historical pet peeve along the line of Frank's STD_INPUT is IR1045, disambiguating single quotes from character literals lexically, as in:

    b <= std_logic_vector'('0','1','1','0');

    While the standard similarly (to the parenthesis issue) gives permission (15.3):

    "In some cases an explicit separator is required to separate adjacent lexical elements (namely when, without separation, interpretation as a single lexical element is possible)."

    Issue Report 1045 was never adopted but explains how to disambiguate. The technique is widely used (I did a survey) but not expressed in the standard, where a natural tendency to a certain paranoia expressed itself as viewing the lack as supporting a zero sum competition stance.

    There was a similar issue for Ada95, widely publicized although I don't recall the AI number. In actuality there aren't enough tool authors especially as the standards increase in volume over time, to oil all the small squeaks. We see the disgruntled start up competing HDL language standards instead although some large number of those efforts fall the wayside.
    Dio Gratia, Sep 18, 2013
    #7
  8. valtih1978

    Andy Guest

    Thanks, Dio Gratia.

    I missed the distinction between [] and {} in the BNF.

    Your response is most helpful and informative.

    Andy
    Andy, Sep 19, 2013
    #8
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