How do I correct this error?

[G Iveco]

Hello all,

I am studying VHDL and came across this problem..
Basically my idea is to write signal "filt" into a file and compare with
reference data.

It worked in RTL but failed in gate-level netlists.


Thank you!





-- Here is declaration part of RTL code.
entity coms_fir is
generic(DATA_WIDTH : integer :=10);
port (
clk_in : in std_logic;
rstn_in : in std_logic;

adc_ena_in : in std_logic;
adc_in : in signed(DATA_WIDTH-1 downto 0);
agc_gain_in : in signed(2 downto 0); -- gain up of 1, 2, 4, 8, ... 128

filt_rdy_out : out std_logic;
filt_out : out signed(DATA_WIDTH-1 downto 0)
);
end coms_fir;


-- Here is declaration of synthesized netlist out of Xilinx.
-- In RTL design, agc_gain_in, adc_in and filt_out are Signed.
-- which are changed to std_logic_vector.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity coms_fir is
port (
clk_in : in STD_LOGIC := 'X';
adc_ena_in : in STD_LOGIC := 'X';
rstn_in : in STD_LOGIC := 'X';
filt_rdy_out : out STD_LOGIC;
agc_gain_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
adc_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
filt_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end coms_fir;



-- Here is my testbench file.
-- I used To_StdLogicVector() to convert agc_gain_in and adc_in..
-- Now the "write" statement can't accept signal "filt"..


library IEEE;
LIBRARY std_developerskit;
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use std.textio.all;
-- use ieee.math_real.uniform;
USE std_developerskit.std_iopak.all;

entity coms_fir_sim is
end coms_fir_sim;

architecture a of coms_fir_sim is
constant DATA_WIDTH : INTEGER :=10;
CONSTANT CLOCK_PERIOD : TIME := 10 ns;
signal clk, rstn : std_logic;
signal adc_ena : std_logic;
signal adc : bit_vector(DATA_WIDTH-1 downto 0);
signal agc_gain : bit_vector(2 downto 0); -- gain up of 1, 2, 4, 8, ...
128

signal filt_rdy : std_logic;
signal filt : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sum_of_prod : bit_vector(DATA_WIDTH+8 downto 0); -- 19-bit
signal sim_status : bit_vector(3 downto 0);

--subtype filt_op is string(1 to 3):=(others=>'0');
--type hex_file is file of filt_op;
--file file_filt_out : hex_file;

-- FILE file_filt_out : hex_file;
-- VARIABLE hex_str : string(1 to 3):=(others=>'0');

file log : text open write_mode is "filt_out.dat";

begin

i_coms_fir: entity work.coms_fir(filt)
-- generic map(DATA_WIDTH)
port map(
clk_in => clk ,
rstn_in => rstn ,

adc_ena_in => adc_ena ,
adc_in => To_StdLogicVector(adc) ,
agc_gain_in => To_StdLogicVector(agc_gain) ,

filt_rdy_out => filt_rdy ,
filt_out => filt
);

feed_data: process is
variable i : integer;
-- FILE file_fir_o : ASCII_TEXT IS "../DAT/fir_out_7.DAT";
variable var_tmp : string(1 to 3);
variable var_tmp_bv : bit_vector (11 downto 0);
variable data_length : bit_vector (11 downto 0);

procedure rcv_data( file_in: in string(1 to 19);
file_out: in string(1 to 25)
) is
FILE file_adc_i : ASCII_TEXT IS file_in;
begin
sim_status <= x"0";
adc_ena <= '0';
-- file_open(file_filt_out, file_out, write_mode);
for i in 1 to 10 loop
wait until clk = '1';
end loop;

fscan (file_adc_i, "%x", var_tmp);
var_tmp_bv := From_HexString(var_tmp);
agc_gain <= var_tmp_bv(2 downto 0);
wait until clk = '1';
fscan (file_adc_i, "%x", var_tmp);
var_tmp_bv := From_HexString(var_tmp);
data_length := var_tmp_bv;
wait until clk = '1';
while NOT endfile(file_adc_i) loop
fscan (file_adc_i, "%x", var_tmp);
var_tmp_bv := From_HexString(var_tmp);
adc <= var_tmp_bv(DATA_WIDTH-1 downto 0);
adc_ena <= '1';
wait until clk = '1';
end loop;

sim_status <= x"1";
for i in 1 to 10 loop
wait until clk = '1';
end loop;
-- file_close(file_filt_out);
sim_status <= x"2";
for i in 1 to 10 loop
wait until clk = '1';
end loop;
sim_status <= x"3";
end procedure rcv_data;

begin

rcv_data("../DAT/adc_in_0.dat", "../DAT/filt_out_sim_0.dat");
rcv_data("../DAT/adc_in_1.dat", "../DAT/filt_out_sim_1.dat");
rcv_data("../DAT/adc_in_2.dat", "../DAT/filt_out_sim_2.dat");
rcv_data("../DAT/adc_in_3.dat", "../DAT/filt_out_sim_3.dat");
rcv_data("../DAT/adc_in_4.dat", "../DAT/filt_out_sim_4.dat");
rcv_data("../DAT/adc_in_5.dat", "../DAT/filt_out_sim_5.dat");
rcv_data("../DAT/adc_in_6.dat", "../DAT/filt_out_sim_6.dat");
rcv_data("../DAT/adc_in_7.dat", "../DAT/filt_out_sim_7.dat");

report "Simulation completed now! "
severity FAILURE;
sim_status <= x"3";

end process feed_data;


process(clk)
variable trace_line : line;
begin
if rising_edge(clk) then
if filt_rdy = '1' then
-- hex_str := To_string(filt,"%3x");
-- fprint(file_filt_out,"%s\n", hex_str);
write(trace_line, to_integer(filt)); -- Modelsim Error Here!
writeline(log, trace_line);
end if;
end if;
end process;


process(clk, rstn)
begin
if rstn = '0' then
sum_of_prod <= (others=>'0');
elsif rising_edge(clk) then
sum_of_prod <=
b"0000_0000_0000_0000_000"; --to_bitvector(i_coms_fir(filt).sum_of_prod);
end if;
end process;


--------------------------------------------------------------------
-- clock and reset stuff
--------------------------------------------------------------------
clock : process
begin
clk <= '1' ;
wait for CLOCK_PERIOD/2;
clk <= '0' ;
wait for CLOCK_PERIOD/2;
end process clock;

reset : process
begin
rstn<='0';
wait for 5*CLOCK_PERIOD;
rstn<='1';
wait;
end process reset;


end a;

 

[Jonathan Bromley]

I am studying VHDL and came across this problem..
Basically my idea is to write signal "filt" into a file and compare with
reference data.

It worked in RTL but failed in gate-level netlists.

I put it to you that it is unreasonable and selfish
to post 150 lines of code and expect others to wade
through it on your behalf. You obviously know how
to code in some other programming language(s), so
presumably you already know how to go about finding
obstinate bugs by cutting back irrelevant code until
you reach the core of the problem. I'm disappointed
that you didn't take the trouble to apply those
skills here.

I also put it to you that you are fibbing. The line
of code you're complaining about either works or
doesn't; I'm guessing that when you tried to simulate
the gate level netlist you were obliged to change the
test bench. So the code that "worked in RTL" (no it
didn't, the testbench isn't RTL) was not the same
code that "failed in gate-level netlists".

Finally, find out about the std_logic_textio package,
which I think will help you.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[G Iveco]

On Sat, 4 Aug 2007 12:32:01 +0800,


Finally, find out about the std_logic_textio package,
which I think will help you.

Sorry for that as I left my computer in a rush..
Now I rephrase my question.

For the "write" statement, how do I write out a stdlogic_vector
a file in unsigned/signed/decimal format?

Following are my extracts from my testbench.


file log : text open write_mode is "filt_out.dat";

signal filt : std_logic_vector(DATA_WIDTH-1 downto 0);



write(trace_line, to_integer(filt)); -- Modelsim Error Here!
writeline(log, trace_line);

 

[Brian Drummond]

For the "write" statement, how do I write out a stdlogic_vector
a file in unsigned/signed/decimal format?

Following are my extracts from my testbench.


file log : text open write_mode is "filt_out.dat";

signal filt : std_logic_vector(DATA_WIDTH-1 downto 0);



write(trace_line, to_integer(filt)); -- Modelsim Error Here!
writeline(log, trace_line);

Any particular Modelsim Error, or did Modelsim just report "Error" with
no further information?

- Brian

 

[Mike Treseler]

Sorry for that as I left my computer in a rush..
Now I rephrase my question.

For the "write" statement, how do I write out a stdlogic_vector
a file in unsigned/signed/decimal format?

I would use a modelsim wave or list output and the radix command.

If you absolutely need a file output of your own format,
I suggest that you reread the last sentence in Jonathan's reply.
That's the easy way.

The other way is to convert vectors to a strings before output
using a function like the one below.
Debug by saying:
report "my_vec is :" & vec_image(my_vec);

See http://home.comcast.net/~mike_treseler/ for details.

-- Mike Treseler


-------------------------------------------------------------------------------
function vec_image(arg : std_logic_vector) return string is
-- recursive function call turns ('1','0','1') into "101"
-------------------------------------------------------------------------------
constant arg_norm : std_logic_vector(1 to arg'length) := arg;
constant center : natural := 2; -- 123
variable bit_image : string(1 to 3); -- '0'
variable just_the_number : character;
begin
if (arg'length > 0) then
bit_image := std_logic'image(arg_norm(1)); -- 3 chars: '0'
just_the_number := bit_image(center); -- 1 char 0
return just_the_number -- first digit
& vec_image(arg_norm(2 to arg_norm'length));
-- rest the same way
else
return ""; -- until "the rest" is nothing
end if;
end function vec_image;

 

[Jonathan Bromley]

For the "write" statement, how do I write out a stdlogic_vector
a file in unsigned/signed/decimal format?

Following are my extracts from my testbench.


file log : text open write_mode is "filt_out.dat";

signal filt : std_logic_vector(DATA_WIDTH-1 downto 0);



write(trace_line, to_integer(filt)); -- Modelsim Error Here!
writeline(log, trace_line);

Yeah, there's no "to_integer" function defined over
std_logic_vector. You have many possible choices:
(1) cast the std_logic_vector to numeric_std.(un)signed
and then convert that to integer:
write(trace_line, to_integer(unsigned(filt)));

(2) use the std_logic_textio package, and then
hwrite(trace_line, filt); --- writes in hex

(3) write a custom conversion function, as suggested
by others

Option (3) may be especially interesting if your
value is, in fact, a fixed-point (integer.fraction)
vector rather than a plain integer. Otherwise the
standard approaches should be OK.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[G Iveco]

I would use a modelsim wave or list output and the radix command.

If you absolutely need a file output of your own format,
I suggest that you reread the last sentence in Jonathan's reply.
That's the easy way.

The other way is to convert vectors to a strings before output
using a function like the one below.
Debug by saying:
report "my_vec is :" & vec_image(my_vec);

See http://home.comcast.net/~mike_treseler/ for details.

-- Mike Treseler

THank you for the function.
Yeah waveform is helpful but when designs get large, no choice..

In fact you can try out this handy package!
http://bear.ces.cwru.edu/vhdl/

Library declarations:

library C;
use C.stdio_h.all;