how do you extract carry, borrow and overflow from an adder in vhdl?

Discussion in 'VHDL' started by Rune Christensen, Jan 20, 2005.

  1. Hello

    I'm looking for examples of extracting carry, borrow and overflow from an
    adder in VHDL.

    I have used this code to extract carry:

    architecture Behavioral of freq_meas_and_pps_detection is
    signal counterold : std_logic_vector(26 downto 0);
    signal counternew : std_logic_vector(27 downto 0);
    begin

    counternew <= ('0' & counterold) + 1;
    pps_detected <= not counternew(27);

    p_freq_pps : process(rst, clk)
    begin
    if (rst = '1') then
    freq <= X"FFFF_FF" & "111";
    elsif (clk'event and clk = '1') then
    if (pps_pulse = '1') then
    freq <= counternew(26 downto 0);
    end if;
    end if;

    if (clk'event and clk = '1') then
    if (pps_pulse = '1') then
    counterold <= X"0000_00" & "000";
    -- counternew(27) is identical to carry out
    elsif (counternew(27) = '0') then
    counterold <= counternew(26 downto 0);
    end if;
    end if;

    end process p_freq_pps;

    end Behavioral;

    Is there another way to extract the status flags from an adder? Maybe a more
    easy way?

    Thanks
    Rune Christensen
    Rune Christensen, Jan 20, 2005
    #1
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  2. Re: how do you extract carry, borrow and overflow from an adder invhdl?

    Rune Christensen wrote:

    > I'm looking for examples of extracting carry, borrow and overflow from an
    > adder in VHDL.


    In most cases, I let synthesis handle the carries.
    Consider using the ieee.numeric_std types and functions
    for counts and comparisons. See:

    http://groups-beta.google.com/groups?q=numeric_std count_v

    -- Mike Treseler
    Mike Treseler, Jan 21, 2005
    #2
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  3. Assuming you are letting the synthesiser build the adder (usually a
    good idea, as it will use any optimisations the target hardware may
    offer):

    So something like this:

    constant N : positive := 8; -- Width of the words to add

    signal A, B, C : unsigned(N-1 downto 0);

    A <= B + C; -- Let the tools do the work :)

    Of course, here's the rub: we cannot get access to the carry, etc.
    But, given the state of the B & C inputs to any adder stage, and its A
    output bit, we can deduce the states of carry-in & out.

    signal CY_IN, CY_OUT, OFLO : std_logic;

    FLAGS : process(A, B, C)
    variable BITS : unsigned(2 downto 0);
    variable CF : unsigned(1 downto 0); -- CIN, COUT
    begin
    BITS := (A(N-1), B(N-1), C(N-1));
    case BITS is
    when "001" => CF <= "11";
    when "010" => CF <= "11";
    when "011" => CF <= "10";
    when "100" => CF <= "01";
    when "111" => CF <= "11";
    when others => CF <= "00";
    end case;
    CY_IN <= CF(0);
    CY_OUT <= CF(1);
    OFLO <= CF(1) xor CF(0);
    end process;

    If I've just done your assignment for you, I expect to share the
    credit :)

    Mike Treseler <> wrote:

    :Rune Christensen wrote:
    :
    :> I'm looking for examples of extracting carry, borrow and overflow from an
    :> adder in VHDL.
    :
    :In most cases, I let synthesis handle the carries.
    :Consider using the ieee.numeric_std types and functions
    :for counts and comparisons. See:
    :
    :http://groups-beta.google.com/groups?q=numeric_std count_v
    :
    : -- Mike Treseler
    David R Brooks, Jan 22, 2005
    #3
  4. "David R Brooks" <> skrev i en meddelelse
    news:...
    > Assuming you are letting the synthesiser build the adder (usually a
    > good idea, as it will use any optimisations the target hardware may
    > offer):
    >
    > So something like this:
    >
    > constant N : positive := 8; -- Width of the words to add
    >
    > signal A, B, C : unsigned(N-1 downto 0);
    >
    > A <= B + C; -- Let the tools do the work :)
    >
    > Of course, here's the rub: we cannot get access to the carry, etc.
    > But, given the state of the B & C inputs to any adder stage, and its A
    > output bit, we can deduce the states of carry-in & out.
    >
    > signal CY_IN, CY_OUT, OFLO : std_logic;
    >
    > FLAGS : process(A, B, C)
    > variable BITS : unsigned(2 downto 0);
    > variable CF : unsigned(1 downto 0); -- CIN, COUT
    > begin
    > BITS := (A(N-1), B(N-1), C(N-1));
    > case BITS is
    > when "001" => CF <= "11";
    > when "010" => CF <= "11";
    > when "011" => CF <= "10";
    > when "100" => CF <= "01";
    > when "111" => CF <= "11";
    > when others => CF <= "00";
    > end case;
    > CY_IN <= CF(0);
    > CY_OUT <= CF(1);
    > OFLO <= CF(1) xor CF(0);
    > end process;
    >
    > If I've just done your assignment for you, I expect to share the
    > credit :)
    >
    > Mike Treseler <> wrote:
    >
    > :Rune Christensen wrote:
    > :
    > :> I'm looking for examples of extracting carry, borrow and overflow from
    > an
    > :> adder in VHDL.
    > :
    > :In most cases, I let synthesis handle the carries.
    > :Consider using the ieee.numeric_std types and functions
    > :for counts and comparisons. See:
    > :
    > :http://groups-beta.google.com/groups?q=numeric_std count_v
    > :
    > : -- Mike Treseler
    >


    This is not an assignment but my spare time interest :)

    Thanks
    Rune
    Rune Christensen, Jan 22, 2005
    #4
  5. Looking again (I wrote that code on the fly), it should of course
    read:
    :> when "010" => CF := "11";

    etc., since CF is a variable, not a signal.

    "Rune Christensen" <> wrote:

    [snip]
    :
    :This is not an assignment but my spare time interest :)
    :
    Good luck, then :)
    David R Brooks, Jan 22, 2005
    #5
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