how to break out of for loop

Discussion in 'VHDL' started by bharathbhushan.kn, Mar 11, 2009.

  1. bharathbhushan.kn

    bharathbhushan.kn

    Joined:
    Mar 11, 2009
    Messages:
    1
    Location:
    Florida
    hey guys, i am new to vhdl and was working on my projects, i wanted to use a for loop instead of a while loop and try to break out of the loop in case of a particular condition, can anyone let me know how to do it please?

    and my friend told me that using a while loop may cause problems while synthesizing, can anyone explain why such a thing happens?

    thanks

    :)
    bharathbhushan.kn, Mar 11, 2009
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  2. bharathbhushan.kn

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Im not sure but if my memory serves me well would could it be done with

    FOR i IN 0 to 10 LOOP
    ....
    IF i=5 THEN
    EXIT
    END IF;
    ....
    END LOOP;

    Check this as well: http://www.vdlande.com/VHDL/exits.html

    Your welcome
    jeppe, Mar 11, 2009
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