How to check if ROM got inferred from synth reports

Discussion in 'VHDL' started by Guy_Sweden, Oct 24, 2006.

  1. Guy_Sweden

    Guy_Sweden Guest

    Hello.
    I have been trying to write code that should infer a ROM using Block
    RAMs. The target device is spartan II series FPGA.
    I have come up with the following code which does get synthesized
    properly and also gets synthsized.
    But i wonder if I have been able to acheive my objective of realising
    ROMs using block RAM as the synthesis report never shows anything that
    any block RAM was ever used.

    Heres the code:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;
    USE ieee.numeric_std.all;
    USE ieee.std_logic_unsigned.all;

    ENTITY BLOCKROM_Coeffs IS
    PORT(
    clk : IN std_logic;
    reset : IN std_logic;
    en : IN std_logic;
    addr : IN std_logic_vector(7 downto 0);
    data : OUT std_logic_vector(15 downto 0)
    );

    -- Declarations

    END ENTITY BLOCKROM_Coeffs ;

    --
    ARCHITECTURE blkram_ROM OF BLOCKROM_Coeffs IS

    type rom_type is array(255 downto 0) of std_logic_vector(15 downto 0);
    constant ROM : rom_type:=(others=>X"0000");
    attribute rom_extract : string;
    attribute rom_style : string;
    attribute rom_extract of ROM : constant is "yes";
    attribute rom_style of ROM : constant is "auto";

    BEGIN
    process(clk)
    begin
    if (clk'event and clk = '1') then
    if (en = '1') then
    data <= ROM(conv_integer(addr));
    end if;
    end if;
    end process;
    END ARCHITECTURE blkram_ROM;

    As far as I know, I think it is because I have not used the Block_ram
    attribute in the code..but i've seen a couple of code examples in the
    newsgroup and on the internet and no where have i come accross such an
    attribute for inferriing a ROM out of Block RAMs.

    Second question:
    Ive seen two major methods when inferring memory. One of them talks
    about using library primitives in which there is no definition for the
    architecture of the memory (or may be it is defined somewhere else)..It
    directly instantiates a component for ex. a library primitive for
    inferring a ROM which has a data bus which is 1 bit wide and has a 16
    bit long word is called ROM16X1
    (http://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/lib/lib0363_327.html#wp1001394).
    Does it mean that if I instantiate a component using this library
    primitive then I dont need to worry about the internal architecture
    right? Just use it directly and all works fine and gets synthesized all
    right..isnt it?
    Additionally some of them are called macros whereas some of them are
    called primitives..could some one please shed some light into this.
    (heres the xilinx link abt memory elements :
    http://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/lib/lib0039_6.html
    )

    The second one is directly writing HDL code which is more of a
    behavioral description of what the memory does..

    Whats the difference between the two methods? Additionally do these
    methods work with synthesis tools..
    I've even heard that one has to do different kinds of memory
    initialisations when simulating and when synthesizing..
    Like it would be different when i wanna simulate the behavior using
    modelsim and when Im synthesizing it.
    Theres a lot of scattered information everywhere but no where can i
    find information about what difference does it make with these two
    methods and when is one supposed to be using what.

    Hoping to hear from you
     
    Guy_Sweden, Oct 24, 2006
    #1
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  2. Mike Treseler, Oct 24, 2006
    #2
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  3. Guy_Sweden

    Guy_Sweden Guest

    Hello.
    The links u sent never seem to open. Would u please provide me with
    alternatives.
    Best regards,
    Aijaz.
    Mike Treseler wrote:
    > Guy_Sweden wrote:
    >
    > > I have been trying to write code that should infer a ROM using Block
    > > RAMs. The target device is spartan II series FPGA.

    >
    > Here's one way to go about it:
    >
    > http://home.comcast.net/~mike_treseler/sync_rom.vhd
    > http://home.comcast.net/~mike_treseler/sync_rom_tech.pdf
    > http://home.comcast.net/~mike_treseler/sync_rom_rtl.pdf
    >
    > -- Mike Treseler
     
    Guy_Sweden, Oct 26, 2006
    #3
  4. Guy_Sweden wrote:
    > Hello.
    > The links u sent never seem to open. Would u please provide me with
    > alternatives.


    Some organizations block comcast.
    Try it from home.

    -- Mike Treseler
     
    Mike Treseler, Oct 26, 2006
    #4
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