How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex4 LX 60)

Discussion in 'VHDL' started by olliH, Apr 16, 2009.

  1. olliH

    olliH Guest

    Hi everybody,

    in my design i have a timing problem with an ADC. I have this problem
    since my design has become more dense:
    This is the ADC I'm using: AD677 (http://www.analog.com/static/
    imported-files/data_sheets/AD677.pdf)

    My ADC-Entity has 3 inputs and 3 outputs. (see datasheet)

    BUSY: IN
    SCLK: IN
    SDATA: IN

    CAL: OUT
    CLK: OUT
    SAMPLE: OUT

    How do i now define the relationship between the CLK-output and the
    SCLK-input for example? In the datasheet are the timing-
    specifications.

    Abstract of my *.UCF file:

    NET ADC1_BUSY LOC = C25;
    NET ADC1_SCLK LOC = E24;
    NET ADC1_SDATA LOC = B24;

    NET ADC1_CAL LOC = E14;
    NET ADC1_CLK LOC = D11;
    NET "ADC1_SAMPLE" LOC = F14;


    I hope somebody with some experience in constraining a design can give
    me some hints.
    The only timing constraint i'm using right now is the period
    constraint for the 100 MHz-clock i'm using.
    I'm an absolute beginner in timing-constraint.... In advance thanks a
    lof for your help.

    sincerely yours

    Olli





    Here the whole UCF-File:

    CONFIG STEPPING = "2";


    NET clk LOC = B13;

    NET ADC_reset LOC = G9;
    NET ADC1_BUSY LOC = C25;
    NET ADC1_CAL LOC = E14;
    NET ADC1_CLK LOC = D11;
    NET ADC1_SCLK LOC = E24;
    NET ADC1_SDATA LOC = B24;
    NET ADC2_BUSY LOC = F24;
    NET ADC2_CAL LOC = D13;
    NET ADC2_CLK LOC = D14;
    NET ADC2_SAMPLE LOC = C11;
    NET ADC2_SCLK LOC = C26;
    NET ADC2_SDATA LOC = E23;


    NET DEACTIVATE_N LOC = N25;
    NET MESS_DONE LOC = L26;
    NET MESS_ENABLE LOC = E2;
    NET M_RESET LOC = E1;

    NET DIP_STRING LOC = A4;
    NET DIP_TD_READMODE LOC = B6;
    NET DOUT LOC = C24;

    NET Druck_VCC LOC = F11;
    NET DIN LOC = A23;
    NET MCLK LOC = F16;
    NET SCLK LOC = B23;

    NET MITTLUNG_LED LOC = V25;
    NET MITTLUNG0 LOC = B4;
    NET MITTLUNG1 LOC = C6;

    NET modell_MESSUNG LOC = G10;


    NET SER_IN_0 LOC = U4;
    NET SER_IN_1 LOC = AA11;
    NET SER_OUT_0 LOC = V4;
    NET SER_OUT_1 LOC = AC11;
    NET "SER_OUT_2" LOC = AC15;
    NET "SER_IN_2" LOC = AC14;
    NET SHIFT_5_TO_3<7> LOC = AC12;
    NET SHIFT_5_TO_3<6> LOC = AA13;
    NET SHIFT_5_TO_3<5> LOC = AD13;
    NET SHIFT_5_TO_3<4> LOC = AB13;
    NET SHIFT_5_TO_3<3> LOC = AC13;
    NET SHIFT_5_TO_3<2> LOC = AA14;
    NET SHIFT_5_TO_3<1> LOC = AD14;
    NET SHIFT_5_TO_3<0> LOC = AB14;
    NET TASTER1 LOC = D2;
    NET TASTER2 LOC = D1;
    NET TD_out LOC = F12;
    NET TD_out2 LOC = F13;
    NET TD_VCC LOC = D16;
    NET TD_VCC2 LOC = D15;
    NET URX_LED LOC = K26;
    NET URX_TX_go_to LOC = C10;
    NET "clk" TNM_NET = clk;
    TIMESPEC TS_clk = PERIOD "clk" 10 ns;
    NET "mittlung_LED" LOC = V25;
    NET "ADC1_SAMPLE" LOC = F14;
    NET "EIN_kHZ" LOC = AA15;




    NET "EIN_kHz" LOC = AA15;
    NET "pin_x" LOC = AD25;
    NET "pin_y" LOC = AC19;
    NET "pin_z" LOC = AD19;
    NET "sync" LOC = AC16;
    NET "sendclk" LOC = AA16;
    olliH, Apr 16, 2009
    #1
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  2. olliH

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    While I'm not an expert, I believe you want to set the 'Pad to Setup for Source Synchronous' timing constraint in this case. This is set in the Constraints Editor (<User Constraints><Set timing constraints>) in ISE 8.2.

    The Xilinx help has some very useful examples on helping to define items such as this.

    John
    JohnDuq, Apr 17, 2009
    #2
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