Howto Create a library from vhdl source with design compiler ?

[Nikolaos Kefalas]

I have created a vhdl package mylib and i want to compile it into a
library with synopsys design compiler, to able to use them as a library
in my vhdl designs.

For example in another design:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library my_lib;
use my_lib.my_lib.all;

I am newby with design compiler and i got confused reading the manuals .

Many thanks
nkef

 

[Mike Treseler]

I have created a vhdl package mylib and i want to compile it into a
library with synopsys design compiler, to able to use them as a library
in my vhdl designs.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library my_lib;
-- use my_lib.my_lib.all;

use work.my_lib.all;

-- Mike Treseler

 

[Kai Harrekilde-Petersen]

use work.my_lib.all;

Design Compiler understands multiple VHDL libraries - albeit not very
well. We used A LOT of different libraries (much to Synopsys chagrin)
at Vitesse.

As I recall, if you want to compile my_package into my_lib you have to
pass "-work my_lib" to the compile function in DC (we had lots of
scripts around the basic DC functions, so my memory is quite hazy
here).


Kai