Infering a sequential in RTL

[rohit.nadig]

Dear Comrades,

I am a newbie to VHDL, and I am curious to know how sequentials are
"infered" in the language. Since everything is a signal (as against
verilog, where you can have explicit register declarations), how does
the language determine which signals will be implemented as registers
and which signals wont.

Certainly, an RTL coder who codes RTL in VHDL would not want to see a
surprisingly large number of sequentials in his design.

Thank you,
Rohit

 

[Jan Decaluwe]

Dear Comrades,

I am a newbie to VHDL, and I am curious to know how sequentials are
"infered" in the language. Since everything is a signal (as against
verilog, where you can have explicit register declarations), how does
the language determine which signals will be implemented as registers
and which signals wont.

Verilog doesn't work like you suggest. Basically, "reg" is a misnomer.
Whether or not actual registers are inferred from Verilog regs depends
entirely on how they are used.

The situation is similar (but not identical) in VHDL. Whether or not
registers are inferred, depends on how VHDL signals and variables are
used.

Certainly, an RTL coder who codes RTL in VHDL would not want to see a
surprisingly large number of sequentials in his design.

He wouldn't want to be suprized in either language. To avoid that,
there's no other way than understanding the language semantics.
BTW, this may seem easier in Verilog but it is easier in VHDL.

Regards, Jan

 

[Mike Treseler]

I am a newbie to VHDL, and I am curious to know how sequentials are
"infered" in the language. Since everything is a signal (as against
verilog, where you can have explicit register declarations), how does
the language determine which signals will be implemented as registers
and which signals wont.

Certainly, an RTL coder who codes RTL in VHDL would not want to see a
surprisingly large number of sequentials in his design.

I'm one HDL coder who doesn't worry about that
because I have worked out templates and
design rules for all the synthesis tools
that I care about. I spend
most of my time on in the editor/simulator.

-- Mike Treseler


PS: I think Andy said it best:
"I believe one is better off focusing on the
behavioral (temporal and logical) description and getting it right, and
not paying so much attention to specific gates and registers which will
not exist in the final result anyway"

 

[KJ]

Dear Comrades,

I am a newbie to VHDL, and I am curious to know how sequentials are
"infered" in the language.

Any signal inside the 'if statement' (Sig1 and Sig2 being examples) will be
a register...it's not difficult at all to figure out which signals are
registers.
process(Clock)
begin
if rising_edge(Clock) then <-- This is the line that infers flip flop
Sig1 <= This or That;
Sig2 <= not This;
end if;
end process;

Since everything is a signal

Except for variables that is.

(as against
verilog, where you can have explicit register declarations), how does
the language determine which signals will be implemented as registers
and which signals wont.

By interpreting the source code that you write....see above....same thing
happens in Verilog or any other language (Abel, Minc). The compiler
interprets the code according to the specification of the language and
figures out which are combinatorial and which are registered, which are
memories, etc.

Certainly, an RTL coder who codes RTL in VHDL would not want to see a
surprisingly large number of sequentials in his design.

The "RTL coder" who is surprised probably doesn't deserve even the dubious
title of "RTL coder"...and most certainly would not have earned any title
with the word 'engineer' in it.

KJ

 

[Andy]

Registers and latches are inferred from code behavior that requires
remembering a previous value. Combinatiorial logic is inferred from
behavior that is based solely on the current value of input signals.

Since signal values are only updated when the process suspends, any
references to signals assigned in a clocked process are references to
the output of a register.

References to signals assigned in a combinatorial process may be
references to the combinatorial value, or to a latched value if the
most recent execution of that process did not result in an assignment
to that signal (i.e. the latch "remembers" the previous state, but
there is no clock, so it must be a latch and not a register)

With variables, it gets a little more tricky, but the code, and the
resulting hardware, behaves more like the code reads (like SW), in that
references after assignments are to the combinatorial value, but
references prior to any assignment are to a remembered,
registered/latched value, depending on whether the process is
clocked/combinatorial, respectively.

Note that vhdl variables for synthesis are not accessible from outside
the process in which they are declared, so while they behave somewhat
like verilog non-blocking signal assignments, there is no ambiguity due
to undefined order of execution of multiple processes. Therefore it is
safe to use variables for registers and combinatorial logic, or even
both with the same variable (remember, it is the reference that
determines register/combo, not the variable itself).

Andy