Is floating_pkg (VHDL-2006) synthesizable ?

Discussion in 'VHDL' started by Ved, Nov 3, 2006.

  1. Ved

    Ved Guest

    Hi
    I have been using the floating package(David Bishop) without any
    problem in modelsim for simulation. ( http://www.eda-stds.org/fphdl/ )
    But when I put them for synthesis I got compilation errors in
    synplicity synplify pro in the float_pkg_c.vhd .
    I am pasting the errors below.

    Do I need to make any changes in the float_pkg_c for synthesis ?

    Please help.

    Regards
    Ved
    -------------------------------------------------------------------------------
    #Build: Synplify Pro 8.6.1, Build 013R, Jun 5 2006

    #install: C:\Program Files\Synplicity\fpga_861

    #OS: Windows XP 5.1

    #Hostname: FPGA_STATION


    #Tue Oct 31 11:35:03 2006


    $ Start of Compile

    #Tue Oct 31 11:35:03 2006


    Synplicity VHDL Compiler, version 3.6t, Build 139R, built Jun 15 2006

    Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved


    @N:CD720 : std.vhd(123) | Setting time resolution to ns

    @N: : loop_filter.vhd(6) | Top entity is set to loop_filter.

    @E:CD415 : float_pkg_c.vhdl(877) | Expecting keyword return

    @E:CD415 : float_pkg_c.vhdl(988) | Expecting keyword is

    @E:CD200 : float_pkg_c.vhdl(6759) | Misspelled variable, signal or
    procedure name?

    @E:CD415 : float_pkg_c.vhdl(6858) | Expecting keyword is

    4 errors parsing file D:\temp\loop_filter_temp\float_pkg_c.vhdl

    @END

    4 errors parsing file D:\temp\loop_filter_temp\loop_filter.vhd

    @END

    @E: : | Parse errors encountered - exiting

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    # Tue Oct 31 11:35:03 2006
     
    Ved, Nov 3, 2006
    #1
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  2. Ved

    David Bishop Guest

    Ved wrote:
    > Hi
    > I have been using the floating package(David Bishop) without any
    > problem in modelsim for simulation. ( http://www.eda-stds.org/fphdl/ )
    > But when I put them for synthesis I got compilation errors in
    > synplicity synplify pro in the float_pkg_c.vhd .
    > I am pasting the errors below.
    >
    > Do I need to make any changes in the float_pkg_c for synthesis ?
    >
    > Please help.


    The syntax which Synplify Pro is having problems with is this:
    -- rtl_synthesis off
    -- pragma synthesis_off
    ......
    alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
    alias BREAD is READ [LINE, UNRESOLVED_float];

    Two ways to fix.
    1) Comment out the "alias" statements (they are not used internally)
    2) Switch to version 8.6.2 of Synplify_pro, which supports these aliases.

    > Regards
    > Ved
    > -------------------------------------------------------------------------------
    > #Build: Synplify Pro 8.6.1, Build 013R, Jun 5 2006
    >
    > #install: C:\Program Files\Synplicity\fpga_861
    >
    > #OS: Windows XP 5.1
    >
    > #Hostname: FPGA_STATION
    >
    >
    > #Tue Oct 31 11:35:03 2006
    >
    >
    > $ Start of Compile
    >
    > #Tue Oct 31 11:35:03 2006
    >
    >
    > Synplicity VHDL Compiler, version 3.6t, Build 139R, built Jun 15 2006
    >
    > Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
    >
    >
    > @N:CD720 : std.vhd(123) | Setting time resolution to ns
    >
    > @N: : loop_filter.vhd(6) | Top entity is set to loop_filter.
    >
    > @E:CD415 : float_pkg_c.vhdl(877) | Expecting keyword return
    >
    > @E:CD415 : float_pkg_c.vhdl(988) | Expecting keyword is
    >
    > @E:CD200 : float_pkg_c.vhdl(6759) | Misspelled variable, signal or
    > procedure name?
    >
    > @E:CD415 : float_pkg_c.vhdl(6858) | Expecting keyword is
    >
    > 4 errors parsing file D:\temp\loop_filter_temp\float_pkg_c.vhdl
    >
    > @END
    >
    > 4 errors parsing file D:\temp\loop_filter_temp\loop_filter.vhd
    >
    > @END
    >
    > @E: : | Parse errors encountered - exiting
    >
    > Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    >
    > # Tue Oct 31 11:35:03 2006
    >
     
    David Bishop, Nov 5, 2006
    #2
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  3. Ved

    Ved Guest

    Hi David ,
    I tried both the ways :
    Both the ways have problem with DEALLOCATE.
    I am pasting error log generated by synplifyPro8.6.2

    ------------------------------------------------------------------------------
    #Build: Synplify Pro 8.6.2, Build 013R, Jun 5 2006
    #install: C:\Program Files\Synplicity\fpga_862
    #OS: Windows XP 5.1
    #Hostname: FPGA_STATION

    #Tue Nov 07 12:18:36 2006

    $ Start of Compile
    #Tue Nov 07 12:18:36 2006
    Synplicity VHDL Compiler, version 3.6t, Build 206R, built Aug 8 2006
    Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : loop_filter.vhd(6) | Top entity is set to loop_filter.
    @E:CD415 : float_pkg_c.vhdl(877) | Expecting keyword return
    @E:CD415 : float_pkg_c.vhdl(988) | Expecting keyword is
    @E:CD200 : float_pkg_c.vhdl(6759) | Misspelled variable, signal or
    procedure name?
    @E:CD415 : float_pkg_c.vhdl(6858) | Expecting keyword is
    4 errors parsing file
    D:\Loop_FIlter\tmp_loop_filter_synth\float_pkg_c.vhdl
    @END
    4 errors parsing file
    D:\Loop_FIlter\tmp_loop_filter_synth\loop_filter.vhd
    @END
    @E: : | Parse errors encountered - exiting
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Nov 07 12:18:36 2006
    -----------------------------------------------------------------------------------------

    What to do now ?

    Thanks
    Ved





    David Bishop wrote:
    > Ved wrote:
    > > Hi
    > > I have been using the floating package(David Bishop) without any
    > > problem in modelsim for simulation. ( http://www.eda-stds.org/fphdl/ )
    > > But when I put them for synthesis I got compilation errors in
    > > synplicity synplify pro in the float_pkg_c.vhd .
    > > I am pasting the errors below.
    > >
    > > Do I need to make any changes in the float_pkg_c for synthesis ?
    > >
    > > Please help.

    >
    > The syntax which Synplify Pro is having problems with is this:
    > -- rtl_synthesis off
    > -- pragma synthesis_off
    > .....
    > alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
    > alias BREAD is READ [LINE, UNRESOLVED_float];
    >
    > Two ways to fix.
    > 1) Comment out the "alias" statements (they are not used internally)
    > 2) Switch to version 8.6.2 of Synplify_pro, which supports these aliases.
    >
    > > Regards
    > > Ved
    > > -------------------------------------------------------------------------------
    > > #Build: Synplify Pro 8.6.1, Build 013R, Jun 5 2006
    > >
    > > #install: C:\Program Files\Synplicity\fpga_861
    > >
    > > #OS: Windows XP 5.1
    > >
    > > #Hostname: FPGA_STATION
    > >
    > >
    > > #Tue Oct 31 11:35:03 2006
    > >
    > >
    > > $ Start of Compile
    > >
    > > #Tue Oct 31 11:35:03 2006
    > >
    > >
    > > Synplicity VHDL Compiler, version 3.6t, Build 139R, built Jun 15 2006
    > >
    > > Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
    > >
    > >
    > > @N:CD720 : std.vhd(123) | Setting time resolution to ns
    > >
    > > @N: : loop_filter.vhd(6) | Top entity is set to loop_filter.
    > >
    > > @E:CD415 : float_pkg_c.vhdl(877) | Expecting keyword return
    > >
    > > @E:CD415 : float_pkg_c.vhdl(988) | Expecting keyword is
    > >
    > > @E:CD200 : float_pkg_c.vhdl(6759) | Misspelled variable, signal or
    > > procedure name?
    > >
    > > @E:CD415 : float_pkg_c.vhdl(6858) | Expecting keyword is
    > >
    > > 4 errors parsing file D:\temp\loop_filter_temp\float_pkg_c.vhdl
    > >
    > > @END
    > >
    > > 4 errors parsing file D:\temp\loop_filter_temp\loop_filter.vhd
    > >
    > > @END
    > >
    > > @E: : | Parse errors encountered - exiting
    > >
    > > Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    > >
    > > # Tue Oct 31 11:35:03 2006
    > >
     
    Ved, Nov 7, 2006
    #3
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