is it possible to have a clockless design synthesizeable?

Discussion in 'VHDL' started by niyander, Jul 29, 2010.

  1. niyander

    niyander Guest

    hi,

    can any one please tell me that is it possible to synthesize a
    clockless design, 100% working?
    few days back i was reading a book on vhdl, there author quoted an
    example of floating point adder and in that example clock was not
    used.

    thanks
     
    niyander, Jul 29, 2010
    #1
    1. Advertising

  2. niyander

    backhus Guest

    On 29 Jul., 03:19, niyander <> wrote:
    > hi,
    >
    > can any one please tell me that is it possible to synthesize a
    > clockless design, 100% working?
    > few days back i was reading a book on vhdl, there author quoted an
    > example of floating point adder and in that example clock was not
    > used.
    >
    > thanks


    Hi,
    sure it is possible.
    I does not always make sense, but possible it is.

    When you are reading abooks on VHDL, keep in mind that there are now
    several target technologies that can be used for HDL designs.
    e.g. CPLDs, FPGAs and ASICs.
    Each has its special strengths and weaknesses.

    Large combinatorical blocks like the mentioned example are good for
    ASICs, where FFs are expensive and silicon is fast with a fine logic
    granulation (down to single gates).
    While in FPGAs FFs are cheap and logic granulation is higher (4 or 6
    input LUTs). Best performance is acheived here by using pipelined
    architectures.

    Have a nice synthesis
    Eilert
     
    backhus, Jul 29, 2010
    #2
    1. Advertising

  3. niyander

    debayan_p

    Joined:
    Jun 2, 2009
    Messages:
    23
    Hey, just think in very simple terms!

    Suppose I design a 4:1 MUX with VHDL/Verilog. Now this design would be clock-less...right?

    Of course Synopsys DA or some FPGA tools would allow you to do the synthesis.
     
    debayan_p, Aug 3, 2010
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Patrick Erich

    modelsim error with synthesizeable VHDL

    Patrick Erich, Nov 24, 2003, in forum: VHDL
    Replies:
    5
    Views:
    3,374
    Jar0d
    Nov 27, 2003
  2. Shashi

    Issues on clockless UART

    Shashi, Apr 21, 2004, in forum: VHDL
    Replies:
    3
    Views:
    714
  3. Shashi
    Replies:
    0
    Views:
    634
    Shashi
    Apr 21, 2004
  4. Replies:
    1
    Views:
    755
    Mike Treseler
    Nov 28, 2005
  5. Harold Aptroot

    "Clockless" computing

    Harold Aptroot, Apr 7, 2011, in forum: VHDL
    Replies:
    1
    Views:
    815
    backhus
    Apr 7, 2011
Loading...

Share This Page