Is this a synthesizable code?

Discussion in 'VHDL' started by vb_thecapt, Mar 22, 2012.

  1. vb_thecapt

    vb_thecapt

    Joined:
    Mar 17, 2012
    Messages:
    3
    Sorry for my newbie question. I have this code that perform a multiplication. Since the operatore '*' is not defined for std_logic_vector, i used integer variable to do so and then convert it to std_logic_vector. The simulations runs well, but is this really synthesizable? Or should i "build" a true multiplier? thanks

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_signed.all;
    
    entity Mul is
        Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);
               y : in  STD_LOGIC_VECTOR (7 downto 0);
               z : out  STD_LOGIC_VECTOR (15 downto 0));
    end Mul ;
    
    architecture Behavioral of Mul is
    
    begin
    
    process (x,y)
    
    variable multiplicand : integer :=0;
    variable multiplier : integer :=0;
    variable product : integer :=0;
    
    begin
    	multiplicand := CONV_INTEGER(x);
    	multiplier := CONV_INTEGER(y);
    	product:= multiplicand*multiplier;
    	
    	z <= CONV_STD_LOGIC_VECTOR(product,16);
    end process;
    
    end Behavioral;
    
    ps: is there a way to know if code is synthesizable without have to try on a board?
    vb_thecapt, Mar 22, 2012
    #1
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