MCU clock divider vs. VHDL divider

Discussion in 'VHDL' started by Matt Clement, Apr 20, 2006.

  1. Matt Clement

    Matt Clement Guest

    Hello

    I have built both a PIC microchip controlled clock divider as well as a CPLD
    clock divider in the past for various projects but was told today that a
    VHDL or discrete logic will always be "cleaner" than one run with a PIC. Is
    this accurate? We are looking to create a clock on the order of 10-20Khz
    from something faster. We are looking to get a very low jitter output.
    Anyone offer any data backing either design?

    thanks
     
    Matt Clement, Apr 20, 2006
    #1
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  2. Matt Clement a écrit :
    > Hello
    >
    > I have built both a PIC microchip controlled clock divider as well as a CPLD
    > clock divider in the past for various projects but was told today that a
    > VHDL or discrete logic will always be "cleaner" than one run with a PIC. Is
    > this accurate? We are looking to create a clock on the order of 10-20Khz
    > from something faster. We are looking to get a very low jitter output.
    > Anyone offer any data backing either design?
    >
    > thanks


    Good evening,

    I do not agree fully with the one "cleaner" than the other. "Differents"
    would be better...

    If you wants an asynchronous divider (driven by original clock), PIC
    cannot handle it. PLD can, but jitter will no be handled very well.

    If you wants a synchronous divider (synchronized to an external clock),
    PIC has its output latched from its main clock. PLD can have a same
    output configuration.
    10..20 kHz can be handled by both them in the same manner if the main
    clock is large enought to use an integer count value for compute wave
    timings.
    But ... you cannot use "C" to write the PLD description, so do not use
    it for pic if you wants to have comparable results :) Use asm.


    Pascal
     
    Pascal Peyremorte, Apr 20, 2006
    #2
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  3. Matt Clement wrote:

    > I have built both a PIC microchip controlled clock divider as well as a CPLD
    > clock divider in the past for various projects but was told today that a
    > VHDL or discrete logic will always be "cleaner" than one run with a PIC. Is
    > this accurate? We are looking to create a clock on the order of 10-20Khz
    > from something faster. We are looking to get a very low jitter output.


    The jitter from a hardware divider
    would be almost as good as the reference clock.
    If that were the only function I needed,
    I would just buy a clock/divider chip.

    The microcontroller output jitter would depend
    on port output execution timing and variable delays
    from caches, irq etc. Do the math.

    -- Mike Treseler
     
    Mike Treseler, Apr 20, 2006
    #3
  4. Mike Treseler <> writes:

    > The microcontroller output jitter would depend
    > on port output execution timing and variable delays
    > from caches, irq etc. Do the math.


    Unless, of course, the MCU has a programmable PWM timer. Many do these
    days.

    -- Marcus
    The Germans have inherited a filthy Saxon culture and no more need be
    said about them.
    -- Mark Ballard, The Register
     
    Marcus Harnisch, Apr 28, 2006
    #4
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