Merging arrays in Modelsim

Discussion in 'VHDL' started by RobertP., Dec 15, 2006.

  1. RobertP.

    RobertP. Guest

    Hi everybody!
    Is there an easy way to merge two signals of type array (for instance
    128 x 8 bits memories) to get one signal array of 128 x 16 bits in Modelsim?

    I'm trying and what I could get was only an array of 256 x 8 (two arays
    one above another), after executing this command:

    add wave {MEM {uut/cr_mem_up uut/cr_mem_lo}}

    Any ideas?

    --
    Regards
    RobertP.
    RobertP., Dec 15, 2006
    #1
    1. Advertising

  2. RobertP. wrote:

    > Is there an easy way to merge two signals of type array (for instance
    > 128 x 8 bits memories) to get one signal array of 128 x 16 bits in
    > Modelsim?


    I would do the merging in the testbench process.

    -- Mike Treseler
    Mike Treseler, Dec 15, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Philipp
    Replies:
    21
    Views:
    1,127
    Philipp
    Jan 20, 2009
  2. Gabriel

    Merging byte arrays

    Gabriel, Apr 11, 2009, in forum: Python
    Replies:
    0
    Views:
    266
    Gabriel
    Apr 11, 2009
  3. ramu
    Replies:
    2
    Views:
    350
    Dann Corbit
    Nov 16, 2009
  4. Chris Chris

    Merging two arrays

    Chris Chris, Sep 22, 2008, in forum: Ruby
    Replies:
    4
    Views:
    140
    Henning Bekel
    Sep 22, 2008
  5. Allen Walker

    Merging two arrays -> array of arrays

    Allen Walker, May 21, 2010, in forum: Ruby
    Replies:
    6
    Views:
    163
    Jesús Gabriel y Galán
    May 21, 2010
Loading...

Share This Page