Modelsim and Warning: NUMERIC_STD.TO_INTEGER: metavalue detected

Discussion in 'VHDL' started by Olaf, Dec 5, 2008.

  1. Olaf

    Olaf Guest

    Hi,

    during my simulation I get the warning above. Anyway I know what it
    means and that is a result of an initializing problem on simulation (and
    even using std_logic ...). To be concrete it occours at t = 0 and t =
    Clk/2. The 2nd warning I get rip up by initialitzing some internal
    architectures signals to '0'.

    Anyway, is there a way to ommit this warnigns at special times, e.g. for
    t=0 ?? It may confuse me on 'bug hunting' ;-)

    Thanks,
    Olaf
     
    Olaf, Dec 5, 2008
    #1
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  2. Olaf

    Tricky Guest

    On 5 Dec, 10:41, Olaf <> wrote:
    > Hi,
    >
    > during my simulation I get the warning above. Anyway I know what it
    > means and that is a result of an initializing problem on simulation (and
    > even using std_logic ...). To be concrete it occours at t = 0 and t =
    > Clk/2. The 2nd warning I get rip up by initialitzing some internal
    > architectures signals to '0'.
    >
    > Anyway, is there a way to ommit this warnigns at special times, e.g. for
    > t=0 ?? It may confuse me on 'bug hunting' ;-)
    >
    > Thanks,
    > Olaf


    You cannot suppress warnings at given times.

    There are 2 options for you:
    1. Give the unsigned/signed value(s) that are giving the problem
    initial values
    2. in modelsim go to Simulate -> Runtime Options -> Suppress warnings
    from IEEE numeric Std Packages. This also blocks the warnings if
    you're converting an integer that's too big for the array (which is
    then truncated). It wont supress warnings from when you try and
    convert a -ve integer into an unsigned though.
     
    Tricky, Dec 5, 2008
    #2
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