# MODULUS operator

Discussion in 'VHDL' started by priya, Nov 15, 2006.

1. ### priyaGuest

hi all
i m using integer data type in VHDL .i have to perform modulo
operation.
but the problem i m facing is that the operand must be a constant
like
A<= (A+1) MOD X
where X is not a constant.
during synthesis i m facing this problem
plz help out soon
one more thing
in case of for loop
for i in 0 to N loop
end loop
again N is sppsed to be fixed

best regards
priya

priya, Nov 15, 2006

2. ### VedGuest

You can use Fixed package availabe at www.eda.org/fphdl , written by
David Bishop.
Its very easy to use and synthesise well with synplify-pro. I havn't
used it on ISE or QUARTUS.

Regards
Ved

priya wrote:
> hi all
> i m using integer data type in VHDL .i have to perform modulo
> operation.
> but the problem i m facing is that the operand must be a constant
> like
> A<= (A+1) MOD X
> where X is not a constant.
> during synthesis i m facing this problem
> plz help out soon
> one more thing
> in case of for loop
> for i in 0 to N loop
> end loop
> again N is sppsed to be fixed
>
> best regards
> priya

Ved, Nov 15, 2006

3. ### AndyGuest

Modulo by a non-integer power of two is not supported by most synthesis
tools.

You could say:

if a + 1 > x then
a <= a + 1 - x;
else
a <= a + 1;
end if;

Which will synthesize for any value of x.

Andy

priya wrote:
> hi all
> i m using integer data type in VHDL .i have to perform modulo
> operation.
> but the problem i m facing is that the operand must be a constant
> like
> A<= (A+1) MOD X
> where X is not a constant.
> during synthesis i m facing this problem
> plz help out soon
> one more thing
> in case of for loop
> for i in 0 to N loop
> end loop
> again N is sppsed to be fixed
>
> best regards
> priya

Andy, Nov 15, 2006
4. ### priyaGuest

hi
i m using Xilinx ISE 7.01.04i
best regards
priya
Ved wrote:
> You can use Fixed package availabe at www.eda.org/fphdl , written by
> David Bishop.
> Its very easy to use and synthesise well with synplify-pro. I havn't
> used it on ISE or QUARTUS.
>
> Regards
> Ved
>
> priya wrote:
> > hi all
> > i m using integer data type in VHDL .i have to perform modulo
> > operation.
> > but the problem i m facing is that the operand must be a constant
> > like
> > A<= (A+1) MOD X
> > where X is not a constant.
> > during synthesis i m facing this problem
> > plz help out soon
> > one more thing
> > in case of for loop
> > for i in 0 to N loop
> > end loop
> > again N is sppsed to be fixed
> >
> > best regards
> > priya

priya, Nov 16, 2006