More synchronization problems

Discussion in 'VHDL' started by Simon, Jan 9, 2004.

  1. Simon

    Simon Guest

    Hi

    I'm having some problems understanding synchronizing my design and reducing
    the metastability. I was hoping someone could answer some of my questions.

    In my design I have a main system clock called SYS_CLK, which comes from a
    programmable timer. This clock runs at 32MHz. An input to my system is a
    NRZI signal. The output is the bit values extracted from the NRZI signal.
    Inside my system I have designed a phase locked loop (to extract the clock
    from the NRZI signal) and I also have a couple more processes which, among
    other things, look for certain bit sequences. My questions are:

    1) Should everything be synchronized to SYS_CLK?
    2) If I pass a signal to a comonent e.g. my phase locked loop, should that
    signal be synchronized inside the component or outside the component?
    3) Is my sychronizer correct (I have included the code at the bottom of this
    message)?
    4) If I synchronize a signal for one component, will I have to synchronize
    the same signal again for another process?
    5) From my 32MHz clock I generate an 8MHz clock for use with the phase
    locked loop. Is the 8MHz clock already synchronized correctly? Can I then
    just pass the 8MHz clock straight to the phase locked loop and use it
    without any extra synchronization?

    Thanks for any help with this as I'm really stuck. If anyone has any
    further advice or pointers concerning this subject then please let me know.

    Thanks again,



    -- Synchronize CLK_IN with SYS_CLK
    entity syncer is
    Port ( RST : in std_logic;
    SYS_CLK : in std_logic;
    CLK_IN : in std_logic;
    SYNC_OUT : out std_logic
    );
    end syncer;

    architecture syncer_arch of syncer is
    signal ff : std_logic;
    begin

    p1 : process(RST, SYS_CLK)
    begin
    if RST = '0' then
    ff <= '0';
    elsif rising_edge(SYS_CLK) then
    ff <= CLK_IN;
    end if;
    end process main;

    p2: process(SYS_CLK)
    begin
    if rising_edge(SYS_CLK) then
    SYNC_OUT <= ff;
    end if;
    end process test;

    end syncer_arch;
     
    Simon, Jan 9, 2004
    #1
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  2. Simon

    tbx135 Guest

    As I understand what you wrote, it sounds like you are recovering clock and
    data from an NRZI serial source. A recovered clock from this stream, using a
    PLL, will have a certain amount of jittering, drift and wander. This may be
    an issue - did you validate the circuit?

    I don't have a clear picture of your data path, I am assuming you want to
    resyncronize to SYS_CLK at some point, is this true? A FIFO may be a quick
    way to accomplish this.

    Next you have an asyncronous reset in your first process, a big no-no. The
    second process has no reset statement, a bigger no-no. I'm suprised the
    synthesis tool isn't whining about the second process.

    Please clarify the above points.

    "Simon" <> wrote in message
    news:btk79q$atr$...
    > Hi
    >
    > I'm having some problems understanding synchronizing my design and

    reducing
    > the metastability. I was hoping someone could answer some of my

    questions.
    >
    > In my design I have a main system clock called SYS_CLK, which comes from a
    > programmable timer. This clock runs at 32MHz. An input to my system is a
    > NRZI signal. The output is the bit values extracted from the NRZI signal.
    > Inside my system I have designed a phase locked loop (to extract the clock
    > from the NRZI signal) and I also have a couple more processes which, among
    > other things, look for certain bit sequences. My questions are:
    >
    > 1) Should everything be synchronized to SYS_CLK?
    > 2) If I pass a signal to a comonent e.g. my phase locked loop, should that
    > signal be synchronized inside the component or outside the component?
    > 3) Is my sychronizer correct (I have included the code at the bottom of

    this
    > message)?
    > 4) If I synchronize a signal for one component, will I have to synchronize
    > the same signal again for another process?
    > 5) From my 32MHz clock I generate an 8MHz clock for use with the phase
    > locked loop. Is the 8MHz clock already synchronized correctly? Can I

    then
    > just pass the 8MHz clock straight to the phase locked loop and use it
    > without any extra synchronization?
    >
    > Thanks for any help with this as I'm really stuck. If anyone has any
    > further advice or pointers concerning this subject then please let me

    know.
    >
    > Thanks again,
    >
    >
    >
    > -- Synchronize CLK_IN with SYS_CLK
    > entity syncer is
    > Port ( RST : in std_logic;
    > SYS_CLK : in std_logic;
    > CLK_IN : in std_logic;
    > SYNC_OUT : out std_logic
    > );
    > end syncer;
    >
    > architecture syncer_arch of syncer is
    > signal ff : std_logic;
    > begin
    >
    > p1 : process(RST, SYS_CLK)
    > begin
    > if RST = '0' then
    > ff <= '0';
    > elsif rising_edge(SYS_CLK) then
    > ff <= CLK_IN;
    > end if;
    > end process main;
    >
    > p2: process(SYS_CLK)
    > begin
    > if rising_edge(SYS_CLK) then
    > SYNC_OUT <= ff;
    > end if;
    > end process test;
    >
    > end syncer_arch;
    >
    >
     
    tbx135, Jan 9, 2004
    #2
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