Multiple sources ??? Example vhdl code - anyone can help ???

[adam8024]

Hello, I'm using Max+plus and when I try to compile this code I've got problem with multiple sources (exactly I've got error 'Signal data1 has multiple sources').
This is a little bit weird because resolved function should be automaticly used by the compiler (at least I think so - STD_LOGIC has got defined resolved function).
So why isn't ??? And I'm looking for any example code that will resolve this error.

Here is full source code:

-- file box1.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box1;

architecture box1 of box1 is
begin
PRrocess(data,c)is
begin
if c='1' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- file box2.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box2;

architecture box2 of box2 is
begin
PRrocess(data,c)is
begin
if c='0' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;


-- file box12.vhd (ERROR ????? - HOW TO WRITE IT ANOTHER WAY ???)
library IEEE;
use IEEE.std_logic_1164.all;

entity box12 is
port (c: in STD_LOGIC;
d : out STD_LOGIC);
end box12;

architecture box12 of box12 is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

signal data1 : STD_LOGIC_VECTOR(7 downto 0);

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

end box12;


I'll we be thankfull for any help.