Need help designing a circuit in Verilog

Discussion in 'VHDL' started by eithriad@gmail.com, Mar 9, 2014.

  1. Guest

    Define and design a circuit which receives a one-bit wave form and shows on its three one-bit outputs, by one clock cycle long positive impulses, the following events:
    -any positive transition of the input signal
    -any negative transition of the input signal
    -any transition of the input signal
    , Mar 9, 2014
    #1
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  2. Τη ΚυÏιακή, 9 ΜαÏτίου 2014 8:09:49 μ.μ. UTC+2, ο χÏήστης Brian Drummond έγÏαψε:
    > On Sun, 09 Mar 2014 03:39:18 -0700, eithriad wrote:
    >
    >
    >
    > > Define and design a circuit which receives a one-bit wave form and shows

    >
    > > on its three one-bit outputs, by one clock cycle long positive impulses,

    >
    > > the following events:

    >
    > > -any positive transition of the input signal -any negative transition of

    >
    > > the input signal -any transition of the input signal

    >
    >
    >
    > comp.lang.vhdl is probably not the best group for a Verilog question.
    >
    >
    >
    > - Brian


    Indeed, the OP should try comp.lang.vhdl, albeit this homework question looks like a classic one.
    Nikolaos Kavvadias, Mar 9, 2014
    #2
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  3. geez I meant comp.lang.verilog, go figure
    Nikolaos Kavvadias, Mar 9, 2014
    #3
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