need help with VHDL code ....ARRAY

[Steewax]

Hi Im a VHDL newbie and I have a problem.Would be great if someone could help me.

I wanna write a program where I can count down 16 counter. I thought I can use an array which includes 16 adresses where I can count down an integer value starting from 40000 in each adress.

Im using Libero and it gives me always this error message:

C:/Actel/Work/UART_APB_state_machine/hdl/Master.vhd(108): ERROR: type
integer does not match with a string literal (VHDL-1276)

Here is the code i wrote:

type array_Timeout is Array (3 downto 0) of integer range 40000 to 0;

signal array_Timeout_Sicherungsmesswerte : array_Timeout;

if array_Timeout_Sicherungsmesswerte("0000") > 0 then
array_Timeout_Sicherungsmesswerte("0000") <= array_Timeout_Sicherungsmesswerte("0000") - 1 ;

else
array_Timeout_Sicherungsmesswerte("0000") <= 0;

I want that if the integer value is bigger than 0 gets counted down. Else it should be set to 0. In this part of the programm I want that the integer value in my first Adress ("0000") gets counted down.

I am not sure if it is possible to declare the adresses of an Array as an st_logic_vector and write in them a integer value.

I would be really thankful if someone could help me.

Thanks

Steve

 

[eliascm]

signal Timeout_Sicherungsmesswerte : integer 0 to 4000;

Timeout : process(Timeout_Sicherungsmesswerte)
begin
if Timeout_Sicherungsmesswerte > 0 then
Timeout_Sicherungsmesswerte <= Timeout_Sicherungsmesswerte - 1;
else
Timeout_Sicherungsmesswerte <= 0;
end if;
end process;

--------------------------------------------------------------------------
Above is my version of what you are trying to do. However it has serious problems. Since it is asynchronous and has no count control it will be zipping through the counts as fast as the device logic speed will allow. You need 2 additions here, in my opinion. You need to make it a synchronous counter, and, depending on how the counter will be used, you may need a control signal that tells the counter when to count. Below is a synchronous version, but with no count control signal. The counter will count continously on each rising edge of clk.

signal Timeout_Sicherungsmesswerte : integer 0 to 4000;

Timeout : process(clk)
begin
if rising_edge(clk) then
if Timeout_Sicherungsmesswerte > 0 then
Timeout_Sicherungsmesswerte <= Timeout_Sicherungsmesswerte - 1;
else
Timeout_Sicherungsmesswerte <= 0;
end if;
end if;
end process;