(newbie) Configure in vhdl (freehdl)

Discussion in 'VHDL' started by Javier M Mora (jamarier), Oct 27, 2006.

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    Hi, i'm absolute newbie and i'm trying freehdl as simulator of VHDL (it was
    easiest to install in my gentoo box).

    Below is halfadder.vhdl there are a line with 3 cases. In every try i
    only uncomment one of them:

    In 1st case: I get: "Sorry, only default component binding is currently
    supported. No default binding for component halfadder found!" (it's
    normal, no configure binding).

    In 2nd case: I get: "halfadder is not a entity" Why? halfadder it's an
    entity. It's a little above :)

    In 3rd case: I reference halfadder inside its package: "work". but in
    this time freehdl-v2cc fails an assertion (break with error message) :-(

    I can run than file if I use 1st case and use
    - --relaxed-component-visibility option in gvhdl. But i think that is
    "cheat".

    How can I set binding between architecture and components?

    If the problem is freehdl is too unstable, my second choice is use
    Alliance but it appears difficult to use.

    What do you think about?

    Thanks, javier m mora

    - ----------8<---------- halfadder.vhdl
    entity halfadder is
    port (x,y: in bit;
    s,c: out bit);
    end entity halfadder;

    architecture RTL of halfadder is
    begin
    s <= x xor y after 10ns;
    c <= x and y after 20ns;
    end architecture RTL;

    entity test_halfadder is
    end entity test_halfadder;

    architecture test_halfadder of test_halfadder is
    signal a,b: bit;
    signal s,c: bit;
    component halfadder
    port (x,y:in bit; s,c:eek:ut bit);
    end component;
    - -- --1st case
    - -- for all: halfadder use entity halfadder(RTL); --2nd case
    - -- for all: halfadder use entity work.halfadder(RTL); --3rd case
    begin
    U1: halfadder port map (a,b,s,c);
    a <= '1' after 50ns, '0' after 100ns;
    b <= '1' after 0ns, '0' after 75ns;
    end architecture test_halfadder;
    - ----------8<---------- end halfadder.vhdl
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    Javier M Mora (jamarier), Oct 27, 2006
    #1
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  2. Javier M Mora (jamarier) wrote:

    > -----BEGIN PGP SIGNED MESSAGE-----
    > Hash: SHA1
    >
    > Hi, i'm absolute newbie and i'm trying freehdl as simulator of VHDL
    > (it was easiest to install in my gentoo box).
    >
    > Below is halfadder.vhdl there are a line with 3 cases. In every try
    > i only uncomment one of them:
    >
    > In 1st case: I get: "Sorry, only default component binding is
    > currently supported. No default binding for component halfadder
    > found!" (it's normal, no configure binding).
    >
    > In 2nd case: I get: "halfadder is not a entity" Why? halfadder it's
    > an entity. It's a little above :)
    >
    > In 3rd case: I reference halfadder inside its package: "work". but


    "work" is not a package, it is a library.
    > in this time freehdl-v2cc fails an assertion (break with error
    > message) :-(
    >
    > I can run than file if I use 1st case and use
    > - --relaxed-component-visibility option in gvhdl. But i think that
    > is "cheat".
    >
    > How can I set binding between architecture and components?


    My preferred way is to use a configuration declaration. This is a
    separate design unit (design units are: entity, architecture,
    package, package body and configuration).

    What you use in you example is a configuration specification. It is
    not a separate design unit, so there can only be one configuration
    specification. Using configuration declarations, there can be more
    than one, e.g. for using different implementations of a design.

    The configuration declaration for your testbench would be (untested):

    CONFIGURATION test_halfadder_cfg OF test_halfadder IS
    FOR test_halfadder_arch
    FOR ALL: test_halfadder
    USE ENTITY work.halfadder(rtl);
    END FOR;
    END FOR;
    END CONFIGURATION test_halfadder_cfg;

    It is test_halfadder_cfg that you need to load into you simulator.

    By the way: you should rename the architecture of test_halfadder (to
    something like test_halfadder_arch, behav or simply arch). I would
    not expect it to be legal to name an entity and architecture the
    same. And even if it was, I would not recommend it.


    > If the problem is freehdl is too unstable, my second choice is use
    > Alliance but it appears difficult to use.


    I do not have any experience with either of them. So I don't know if
    my solution will work. It is legal VHDL, but I do not know whether
    freehdl supports configuration declarations.

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
    Paul Uiterlinden, Oct 29, 2006
    #2
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