number of bits needed

[skatoulas]

Hi all,

I've got the following problem. I've got a generic integer input to an
entity that defines the number of S-R flip flops to be created.

generic ( num_of_nodes : integer := 10);
port ( parent_in : in std_logic_vector(num_of_nodes - 2 downto 0));
parent_store : process
begin
wait until clk'event and clk='1';
if reset = '1' then
Q <= (others=>'0');
else
for i in num_of_nodes - 2 downto 0 loop
if parent_in(i) = '1' then
Q(i) <= '1';
end if;
end loop;
end if;
end process;

Then I want to count how many 1's there are in the signal Q. This would
like like

compute_parent_states : process(Q)
variable temp_N : std_logic_vector(some_size downto 0);
begin
temp_N := (others=>'0');
for i in num_of_nodes - 2 downto 0 loop
if Q(i) = '1' then
temp_N := unsigned(temp_N) + 1;
end if;
end loop;
end process;

The problem here is that there have to be ceiling(log2(num_of_nodes-1))
bits in the temp_N signal but I don't know of a way to compute this. It
doesn't have to be syntheizable hardware, I just want it to be computed
during synthesis as I then want to create a counter that counts from 0
to 2^some_size-1. I'd appreciate any hints.

Cheers

 

[Mike Treseler]

I've got the following problem. I've got a generic integer input to an
entity that defines the number of S-R flip flops to be created.

Consider a higher level description of your logic.

The problem here is that there have to be ceiling(log2(num_of_nodes-1))

http://groups-beta.google.com/groups?q=round+ceil_log2

-- Mike Treseler

 

[skatoulas]

But of course... Thank you