Pipelined binary encoder

[Fred Bartoli]

Hello,

I need to include in my design a wide (128 inputs and later 256 inputs) one
hot to binary encoder.
It has to run at 100MHz so I'm looking for a pipelined one (latency is no
pb).
I've searched almost everywhere to not avail and can't come with a good
solution by myself.

Does someone have hints or can point me in the right direction ?

Oh, we need 2 of them and they will be implemented in an APEX 20KE.
There will be lots of other stuff too, so it has to be pretty size
efficient.

 

[Jonathan Bromley]

Hello,

I need to include in my design a wide (128 inputs and later 256 inputs) one
hot to binary encoder.
It has to run at 100MHz so I'm looking for a pipelined one (latency is no
pb).
I've searched almost everywhere to not avail and can't come with a good
solution by myself.

Does someone have hints or can point me in the right direction ?

Oh, we need 2 of them and they will be implemented in an APEX 20KE.
There will be lots of other stuff too, so it has to be pretty size
efficient.

A 256-to-8 one-hot to binary encoder is just eight 128-input OR gates,
right? And a wide OR gate is easy to pipeline - just a tree of
smaller OR gates, with pipeline registers at whatever levels you choose.
The trick is to find a nice way to code it in VHDL. Recursive
is pretty, though not all tools do a good job on recursive
hardware descriptions.

You may even find that the 128-in OR gate is fast enough without
pipelining, though I doubt it.

If you need to check that the input code is truly one-hot,
things are much tougher.