port declaration problem

Discussion in 'VHDL' started by chris, Nov 13, 2003.

  1. chris

    chris Guest

    I tried to declare an output port of my entity as an array and the
    compiler don't want it.

    Here comes an example :

    ------------
    entity test is
    generic (
    a : positive := 8;
    b : positive := 8
    );
    port (
    e : in std_logic;
    s : out array(a downto 0) of std_logic_vector(b downto 0)
    );
    end entity test;
    ------------

    Do I made a syntaxe error ?
    Is someone can give me a possible solution to go around this problem ?

    Thanks.
    Christophe
     
    chris, Nov 13, 2003
    #1
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  2. chris

    Brent Hayhoe Guest

    chris wrote:

    > I tried to declare an output port of my entity as an array and the
    > compiler don't want it.
    >
    > Here comes an example :


    Chris, you need to define your array as a type within a package and use that
    package in your entitiy.

    package MY_PKG is
    constant A_c : Positive := 8;
    constant B_c : Positive := 8;
    type MY_SLV_a is array(A_c downto 0) of Std_Logic_Vector(B_c downto 0)
    end package MY_PKG;
    >
    > ------------

    use work.MY_PKG.all
    > entity test is
    > generic (

    A_g : Positive := A_c;
    B_g : Positive := B_c
    > );
    > port (
    > e : in std_logic;

    S : out MY_SLV_a
    > );
    > end entity test;
    > ------------
    >
    > Do I made a syntaxe error ?
    > Is someone can give me a possible solution to go around this problem ?
    >
    > Thanks.
    > Christophe


    --

    Regards,

    Brent Hayhoe.

    Aftonroy Limited
    Email: <A
    HREF="mailto:">
     
    Brent Hayhoe, Nov 13, 2003
    #2
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  3. chris

    Alan Fitch Guest

    "chris" <> wrote in message
    news:...
    > I tried to declare an output port of my entity as an array and the
    > compiler don't want it.
    >
    > Here comes an example :
    >
    > ------------
    > entity test is
    > generic (
    > a : positive := 8;
    > b : positive := 8
    > );
    > port (
    > e : in std_logic;
    > s : out array(a downto 0) of std_logic_vector(b downto 0)
    > );
    > end entity test;
    > ------------
    >
    > Do I made a syntaxe error ?
    > Is someone can give me a possible solution to go around this problem

    ?
    >


    Yes,
    you can't create an array type "on the fly" like that - you have
    to create a type first. Because it's being used on a port, you need
    a package. Unfortunately that makes it tricky to use a generic for
    b (the width of the std_logic_vector), though you can make "a" a
    generic as follows.

    library IEEE;
    use IEEE.std_logic_1164.all;

    package P is

    subtype SLVT is std_logic_vector(8 downto 0);

    -- note array element *must be constrained*
    type SLVArrayT is array (natural range <>) of SLVT;
    end;

    library IEEE;
    use IEEE.std_logic_1164.all;
    use work.P.all;
    entity test is
    generic (a : positive := 8);
    port (
    e : in std_logic;
    s : out SLVArrayT(a downto 0)
    );
    end;

    architecture a of test is

    -- and here's b deduced from SLVT;
    constant b : positive := s'LENGTH;
    begin

    ...


    kind regards

    Alan

    p.s. I haven't compiled this, but it *should* work.
    Sometimes analysis fails if S'LENGTH is not considered
    to be locally static to initialize the constant.

    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

    Fax: +44 (0)1425 471573 Web:
    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Nov 13, 2003
    #3
  4. chris

    chris Guest

    Is this means that there is no way to declare b as a generic parameter ?

    Brent Hayhoe <> wrote in message news:<bp0c1u$gnv$>...
    > chris wrote:
    >
    > > I tried to declare an output port of my entity as an array and the
    > > compiler don't want it.
    > >
    > > Here comes an example :

    >
    > Chris, you need to define your array as a type within a package and use that
    > package in your entitiy.
    >
    > package MY_PKG is
    > constant A_c : Positive := 8;
    > constant B_c : Positive := 8;
    > type MY_SLV_a is array(A_c downto 0) of Std_Logic_Vector(B_c downto 0)
    > end package MY_PKG;
    > >
    > > ------------

    > use work.MY_PKG.all
    > > entity test is
    > > generic (

    > A_g : Positive := A_c;
    > B_g : Positive := B_c
    > > );
    > > port (
    > > e : in std_logic;

    > S : out MY_SLV_a
    > > );
    > > end entity test;
    > > ------------
    > >
    > > Do I made a syntaxe error ?
    > > Is someone can give me a possible solution to go around this problem ?
    > >
    > > Thanks.
    > > Christophe

    >
    > --
    >
    > Regards,
    >
    > Brent Hayhoe.
    >
    > Aftonroy Limited
    > Email: <A
    > HREF="mailto:">
     
    chris, Nov 14, 2003
    #4
  5. chris

    Brent Hayhoe Guest

    chris wrote:
    > Is this means that there is no way to declare b as a generic parameter ?


    No, and this is because the LRM doesn't allow unconstrained arrays of
    unconstrained arrays. I thought this might have been changing in VHDL-200x, but
    can find no reference to it on www.eda.org.

    The first way you tried to use it within the entity port is called an anonymous
    array and these are also illegal in VHDL.

    There is no (current) way of passing both sizes of a 2 dimensional array
    generically into an entity. I have come across this problem when trying to build
    a generic ROM and had to define a maximum size ROM array to pass in through the
    entity port. I then stripped it down locally to the required size within the
    architecture.

    --

    Regards,

    Brent Hayhoe.

    Aftonroy Limited
    Email: <A
    HREF="mailto:">
     
    Brent Hayhoe, Nov 14, 2003
    #5
  6. chris

    Jim Lewis Guest

    Brent,
    >> Is this means that there is no way to declare b as a generic parameter ?

    >
    > No, and this is because the LRM doesn't allow unconstrained arrays of
    > unconstrained arrays. I thought this might have been changing in
    > VHDL-200x, but can find no reference to it on www.eda.org.


    I am also highly interested in this happening.

    It is referenced in some of the documents (as ragged arrays rather
    than arrays of unconstrained arrays). It should be happening under
    the direction of the data types and abstractions group.
    Their web address is:
    http://www.eda.org/vhdl-200x/vhdl-200x-dta/

    There are two ways of making sure this happens.
    1) Keep checking back and make sure it gets on the proposals
    list, and kick people (figuratively) until it does.
    2) Join the working group and help write the proposal
    3) Join the working group and vote for the proposal.

    I am part of the VHDL-200x working group(s). One voice
    cannot guarantee a feature as most of what we do gets
    voted on.

    Cheers,
    Jim Lewis
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Nov 14, 2003
    #6
  7. chris

    Brent Hayhoe Guest

    Hi Jim,

    Jim Lewis wrote:

    > Brent,
    > >> Is this means that there is no way to declare b as a generic

    > parameter ?
    > >
    > > No, and this is because the LRM doesn't allow unconstrained arrays of
    > > unconstrained arrays. I thought this might have been changing in
    > > VHDL-200x, but can find no reference to it on www.eda.org.

    >
    > I am also highly interested in this happening.
    >
    > It is referenced in some of the documents (as ragged arrays rather
    > than arrays of unconstrained arrays). It should be happening under
    > the direction of the data types and abstractions group.
    > Their web address is:
    > http://www.eda.org/vhdl-200x/vhdl-200x-dta/


    Yes, but most of the site (vhdl-200x-dta) isn't up and running yet! It may have
    something to do with Paul Menchini, as I seem to mention talk of him giving up
    things due to some reason, personal or business I don't know which.

    'www.mench.com' although resolving is blank also.

    >
    > There are two ways of making sure this happens.
    > 1) Keep checking back and make sure it gets on the proposals
    > list, and kick people (figuratively) until it does.
    > 2) Join the working group and help write the proposal
    > 3) Join the working group and vote for the proposal.
    >
    > I am part of the VHDL-200x working group(s). One voice
    > cannot guarantee a feature as most of what we do gets
    > voted on.


    I am registered on most of the reflectors, however things are conspiring against
    me. Although I can receive stuff from eda.org, I can't send to it as my ISP
    (Freeserve) or more likely Energis, who handle their ADSL routing, are blocking
    outgoing Email to this domain. Damn SPAM! And getting this reversed is proving
    difficult.

    I have to subscribe via a secondary Email, but so far have not been able to get
    onto the 'dta' or 'env' reflectors. This could be a similar reason as to the
    site not being fully active.

    As to voting, I'm not a member of DASC (or even the IEEE) and as a poor meagre
    freelance design engineer, (currently resting as any thespian would say :) I
    don't know if I can justify the expense presently. But I'll try and drop in my
    2d worth.

    >
    > Cheers,
    > Jim Lewis


    --

    Regards,

    Brent Hayhoe.

    Aftonroy Limited
    Email: <A
    HREF="mailto:">
     
    Brent Hayhoe, Nov 14, 2003
    #7
  8. chris

    Jim Lewis Guest

    Brent,
    >> >> Is this means that there is no way to declare b as a generic

    >> parameter ?
    >> >
    >> > No, and this is because the LRM doesn't allow unconstrained arrays of
    >> > unconstrained arrays. I thought this might have been changing in
    >> > VHDL-200x, but can find no reference to it on www.eda.org.

    >>
    >> I am also highly interested in this happening.
    >>
    >> It is referenced in some of the documents (as ragged arrays rather
    >> than arrays of unconstrained arrays). It should be happening under
    >> the direction of the data types and abstractions group.
    >> Their web address is:
    >> http://www.eda.org/vhdl-200x/vhdl-200x-dta/

    >
    >
    > Yes, but most of the site (vhdl-200x-dta) isn't up and running yet! It
    > may have something to do with Paul Menchini, as I seem to mention talk
    > of him giving up things due to some reason, personal or business I don't
    > know which.


    The DTA webpage needs to be updated. Paul Menchini
    has retired as team leader. Peter Ashenden has taken
    over. Being sensitive to SPAM and newsgroups, if you need
    his email, you can find it by looking through the reflector
    archives on the vhdl-200x websites.

    >>
    >> There are two ways of making sure this happens.
    >> 1) Keep checking back and make sure it gets on the proposals
    >> list, and kick people (figuratively) until it does.
    >> 2) Join the working group and help write the proposal
    >> 3) Join the working group and vote for the proposal.
    >>
    >> I am part of the VHDL-200x working group(s). One voice
    >> cannot guarantee a feature as most of what we do gets
    >> voted on.

    >
    >
    > I am registered on most of the reflectors, however things are conspiring
    > against me. Although I can receive stuff from eda.org, I can't send to
    > it as my ISP (Freeserve) or more likely Energis, who handle their ADSL
    > routing, are blocking outgoing Email to this domain. Damn SPAM! And
    > getting this reversed is proving difficult.
    >
    > I have to subscribe via a secondary Email, but so far have not been able
    > to get onto the 'dta' or 'env' reflectors. This could be a similar
    > reason as to the site not being fully active.


    The eda.org reflectors were down for a couple of days recently.


    > As to voting, I'm not a member of DASC (or even the IEEE) and as a poor
    > meagre freelance design engineer, (currently resting as any thespian
    > would say :) I don't know if I can justify the expense presently. But
    > I'll try and drop in my 2d worth.


    I would recommend voting any way and marking your vote as a
    non-voting member. This would at least be considered as a
    voice from the design community.

    Cheers,
    Jim

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Nov 14, 2003
    #8
  9. chris

    fe Guest

    No, for an array of std_logic_vector but you can define a 2D array of
    std_logic.

    package sl2d_pkg is
    type t_std_logic_2d is array (natural range <>, natural range <>)of
    std_logic;
    end package;

    library work;
    use work.sl2d_pkg.all;

    entity test is
    generic (
    a : positive := 8;
    b : positive := 8
    );
    port (
    e : in std_logic;
    s : out t_std_logic_2d(a-1 downto 0, b-1 downto 0)
    );
    end entity test;

    PS: Don't forget, it's a t_std_logic_2d and not an array of
    std_logic_vector. You can't do things like this s(0) <= slv. You must use a
    for loop (directly or in a function/procedure).
    for i in 0 to b-1 loop
    s(0, i) <= slv(i);
    end loop;

    it's not perfect but in waiting of vhdl200x, it's the only thing you can do
    to use a and b generic.

    regards,
    fe


    "chris" <> wrote in message
    news:...
    > Is this means that there is no way to declare b as a generic parameter ?
    >
    > Brent Hayhoe <> wrote in message

    news:<bp0c1u$gnv$>...
    > > chris wrote:
    > >
    > > > I tried to declare an output port of my entity as an array and the
    > > > compiler don't want it.
    > > >
    > > > Here comes an example :

    > >
    > > Chris, you need to define your array as a type within a package and use

    that
    > > package in your entitiy.
    > >
    > > package MY_PKG is
    > > constant A_c : Positive := 8;
    > > constant B_c : Positive := 8;
    > > type MY_SLV_a is array(A_c downto 0) of Std_Logic_Vector(B_c downto

    0)
    > > end package MY_PKG;
    > > >
    > > > ------------

    > > use work.MY_PKG.all
    > > > entity test is
    > > > generic (

    > > A_g : Positive := A_c;
    > > B_g : Positive := B_c
    > > > );
    > > > port (
    > > > e : in std_logic;

    > > S : out MY_SLV_a
    > > > );
    > > > end entity test;
    > > > ------------
    > > >
    > > > Do I made a syntaxe error ?
    > > > Is someone can give me a possible solution to go around this problem ?
    > > >
    > > > Thanks.
    > > > Christophe

    > >
    > > --
    > >
    > > Regards,
    > >
    > > Brent Hayhoe.
    > >
    > > Aftonroy Limited
    > > Email: <A
    > >

    HREF="mailto:Brent.Hayh&#1
    11;&
    #111;m">
     
    fe, Nov 14, 2003
    #9
  10. chris

    Brent Hayhoe Guest

    Hi Jim

    Jim Lewis wrote:

    > Brent,
    >
    > The eda.org reflectors were down for a couple of days recently.


    Ah, but this is a much more long running problem, and my Emails are actually
    bouncing back with 'domain disallowed' stamped on them!

    >
    > I would recommend voting any way and marking your vote as a
    > non-voting member. This would at least be considered as a
    > voice from the design community.


    I'll bear that in mind, as I've not considered partaking in this manner.

    Thanks for the info.

    --

    Regards,

    Brent Hayhoe.

    Aftonroy Limited
    Email: <A
    HREF="mailto:">
     
    Brent Hayhoe, Nov 14, 2003
    #10
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