Problem in creating dump using Modelsim

Discussion in 'VHDL' started by shakeelsultan, May 7, 2008.

  1. shakeelsultan

    shakeelsultan

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    Hi all;
    I've a processor core written in VHDL & am trying to excute some instructions on this processor, the goal is to generate the activity produced by each instruction, for this I'm using vcd add -r -file filename/object/*, now I want to ask that whether this command has capability to monitor activity on all the internal nets of the design, against a given instruction or I've to add some more switch to 'vcd add'

    Thanks in advance
    Shakeel Sultan
     
    shakeelsultan, May 7, 2008
    #1
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