problem in optimization of top level

Discussion in 'VHDL' started by ashu, Dec 4, 2006.

  1. ashu

    ashu Guest

    dear all,

    my problem is regarding optimization of the code. i have written a top
    level code which is calling say three components....problem is that
    seprately all the components are giving me a max. opreating freq.
    somewhere near to say 200 Mhz but as soon as i used them in a top level
    its comes down to say 30-40 Mhz. what could be the reason ....i m using
    quartus and i also tested the same on synplicity.....

    thanks
    ashwani

    ---------------------------------
    ---------------------------------------
    Library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.std_logic_unsigned.all ;
    use ieee.std_logic_arith.all ;

    entity top_level is

    port(
    pclk,start_in,y_sel: in std_logic ;
    q_sel : in std_logic_vector(2 downto 0) ;

    u1_rom_data : out std_logic_vector(11 downto 0);
    u1_start_out : out std_logic;

    u2_st_qntsig : out std_logic ;
    u2_data_qntsig : out integer range -127 to 127 ;

    st_zzout : out std_logic ;
    zz_out : out std_logic_vector(7 downto 0)
    );


    end top_level ;

    architecture a of top_level is
    ------------- intermediate signals ---------

    signal st_romsig, st_qntsig,st_zzs : std_logic ;
    signal data_int : integer range -2047 to 2047 ;
    signal data_qnt,data_zzs : std_logic_vector(7 downto 0);
    signal data_romsig : std_logic_vector(11 downto 0);
    signal data_qntsig : integer range -127 to 127 ;

    -----------------------------------------------------------------------

    component rom

    port (
    clk,rst : in std_logic ;
    rom_stout : out std_logic ;
    dct_out : out std_logic_vector(11 downto 0)
    ) ;
    end component ;
    -------------------------------------------------------------------------
    component qnt
    port (
    clk,startin : in std_logic ;
    a : in integer range 2047 downto -2047;
    sel : in std_logic_vector ( 2 downto 0);
    sel_Y_cr : in std_logic;
    z : out integer range 127 downto -127;
    startout : out std_logic
    );
    end component ;
    -------------------------------------------------------------------------------
    component zz is

    port
    (
    pclk,start_in : in std_logic ;
    start_out : out std_logic ;
    data_in : in std_logic_vector(7 downto 0) ;
    data_out : out std_logic_vector(7 downto 0)
    ) ;
    end component ;
    ------------------------------------------------------------------------------------------
    begin


    data_int <= conv_integer ( signed(data_romsig) ) ;
    data_qnt <= conv_std_logic_vector (data_qntsig,8) ;

    U1 : rom port map( pclk,start_in,st_romsig,data_romsig);
    U2 : qnt port map(
    pclk,st_romsig,data_int,q_sel,y_sel,data_qntsig,st_qntsig);
    U3 : zz port map( pclk,st_qntsig,st_zzs,data_qnt,data_zzs);

    ---------- output ports to tap the signals -----------------
    u1_rom_data <= data_romsig ;
    u1_start_out <= st_romsig ;
    u2_st_qntsig <= st_qntsig ;
    u2_data_qntsig <= data_qntsig ;
    zz_out <= data_zzs ;




    end a ;
    ashu, Dec 4, 2006
    #1
    1. Advertising

  2. ashu wrote:

    > my problem is regarding optimization of the code. i have written a top
    > level code which is calling say three components....problem is that

    *instancing*

    > seprately all the components are giving me a max. opreating freq.
    > somewhere near to say 200 Mhz but as soon as i used them in a top level
    > its comes down to say 30-40 Mhz. what could be the reason


    Sounds like the system clock is not
    on a global path.

    -- Mike Treseler
    Mike Treseler, Dec 4, 2006
    #2
    1. Advertising

  3. ashu

    A. M. Guest

    Assuming that all three instantiated modules run at higher frequency
    separately, the only reason for lower frequency i would see would be
    the minor logic added to ur top level..maybe the conversion functions
    that u use, adding a worse case path delay causing a reduction in top
    level frequency...



    On Dec 4, 12:49 pm, Mike Treseler <> wrote:
    > ashu wrote:
    > > my problem is regarding optimization of the code. i have written a top
    > > level code which is calling say three components....problem is that *instancing*

    >
    > > seprately all the components are giving me a max. opreating freq.
    > > somewhere near to say 200 Mhz but as soon as i used them in a top level
    > > its comes down to say 30-40 Mhz. what could be the reasonSounds like the system clock is not

    > on a global path.
    >
    > -- Mike Treseler
    A. M., Dec 4, 2006
    #3
  4. ashu

    Andy Guest

    I'm not sure, but this may be your problem:

    Default timing constraints (clock constraints) do not usually cover
    combinatorial IO. So when you synthesized the individual modules, the
    combinatorial IO delay was not used to determine the max clock speed.
    However, when you plumb the modules together, the combinatorial IOs
    from each module become clk-clk delays, which are then covered, and
    determine the slower overall clock speed.

    Andy


    ashu wrote:
    > dear all,
    >
    > my problem is regarding optimization of the code. i have written a top
    > level code which is calling say three components....problem is that
    > seprately all the components are giving me a max. opreating freq.
    > somewhere near to say 200 Mhz but as soon as i used them in a top level
    > its comes down to say 30-40 Mhz. what could be the reason ....i m using
    > quartus and i also tested the same on synplicity.....
    >
    > thanks
    > ashwani
    >
    > ---------------------------------
    > ---------------------------------------
    > Library ieee ;
    > use ieee.std_logic_1164.all ;
    > use ieee.std_logic_unsigned.all ;
    > use ieee.std_logic_arith.all ;
    >
    > entity top_level is
    >
    > port(
    > pclk,start_in,y_sel: in std_logic ;
    > q_sel : in std_logic_vector(2 downto 0) ;
    >
    > u1_rom_data : out std_logic_vector(11 downto 0);
    > u1_start_out : out std_logic;
    >
    > u2_st_qntsig : out std_logic ;
    > u2_data_qntsig : out integer range -127 to 127 ;
    >
    > st_zzout : out std_logic ;
    > zz_out : out std_logic_vector(7 downto 0)
    > );
    >
    >
    > end top_level ;
    >
    > architecture a of top_level is
    > ------------- intermediate signals ---------
    >
    > signal st_romsig, st_qntsig,st_zzs : std_logic ;
    > signal data_int : integer range -2047 to 2047 ;
    > signal data_qnt,data_zzs : std_logic_vector(7 downto 0);
    > signal data_romsig : std_logic_vector(11 downto 0);
    > signal data_qntsig : integer range -127 to 127 ;
    >
    > -----------------------------------------------------------------------
    >
    > component rom
    >
    > port (
    > clk,rst : in std_logic ;
    > rom_stout : out std_logic ;
    > dct_out : out std_logic_vector(11 downto 0)
    > ) ;
    > end component ;
    > -------------------------------------------------------------------------
    > component qnt
    > port (
    > clk,startin : in std_logic ;
    > a : in integer range 2047 downto -2047;
    > sel : in std_logic_vector ( 2 downto 0);
    > sel_Y_cr : in std_logic;
    > z : out integer range 127 downto -127;
    > startout : out std_logic
    > );
    > end component ;
    > -------------------------------------------------------------------------------
    > component zz is
    >
    > port
    > (
    > pclk,start_in : in std_logic ;
    > start_out : out std_logic ;
    > data_in : in std_logic_vector(7 downto 0) ;
    > data_out : out std_logic_vector(7 downto 0)
    > ) ;
    > end component ;
    > ------------------------------------------------------------------------------------------
    > begin
    >
    >
    > data_int <= conv_integer ( signed(data_romsig) ) ;
    > data_qnt <= conv_std_logic_vector (data_qntsig,8) ;
    >
    > U1 : rom port map( pclk,start_in,st_romsig,data_romsig);
    > U2 : qnt port map(
    > pclk,st_romsig,data_int,q_sel,y_sel,data_qntsig,st_qntsig);
    > U3 : zz port map( pclk,st_qntsig,st_zzs,data_qnt,data_zzs);
    >
    > ---------- output ports to tap the signals -----------------
    > u1_rom_data <= data_romsig ;
    > u1_start_out <= st_romsig ;
    > u2_st_qntsig <= st_qntsig ;
    > u2_data_qntsig <= data_qntsig ;
    > zz_out <= data_zzs ;
    >
    >
    >
    >
    > end a ;
    Andy, Dec 5, 2006
    #4
  5. Mike Treseler wrote:

    > ashu wrote:
    >
    >> my problem is regarding optimization of the code. i have written a
    >> top level code which is calling say three components....problem is
    >> that

    > *instancing*


    Shouldn't that be *instantiating*?

    I don't have a copy of Language Reference Manual of English, so
    perhaps you can enlighten me. ;-)

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
    Paul Uiterlinden, Dec 5, 2006
    #5
  6. Paul Uiterlinden wrote:

    >> *instancing*

    >
    > Shouldn't that be *instantiating*?


    That's the common usage, but I like instance
    because it is a transitive verb and is simpler.
    But either one is better than "call" :)

    -- Mike Treseler

    __________________________
    instantiate
    v
    1: represent by an instance; "This word instantiates the usage
    that the linguists claimed to be typical for a certain
    dialect"
    2: find an instance of (a word or particular usage of a word);
    "The linguists could not instantiate this sense of the
    noun that he claimed existed in a certain dialect"


    Instance | In"stance |
    v. t. imp. & p. p. Instanced; p. pr. &
    vb. n. Instancing.
    To mention as a case or example; to refer to; to cite; as, to
    instance a fact. --H. Spenser.
    1913 Webster

    I shall not instance an abstruse author. --Milton.
    1913 Webster
    Mike Treseler, Dec 5, 2006
    #6
  7. Mike Treseler wrote:

    > Paul Uiterlinden wrote:
    >
    >>> *instancing*

    >>
    >> Shouldn't that be *instantiating*?

    >
    > That's the common usage, but I like instance
    > because it is a transitive verb and is simpler.
    > But either one is better than "call" :)


    Definitely!
    Thanks for the explanation.

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
    Paul Uiterlinden, Dec 6, 2006
    #7
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Makis Papapanagiotou
    Replies:
    1
    Views:
    298
    Kevin Goodsell
    Sep 23, 2003
  2. pabbu
    Replies:
    8
    Views:
    707
    Marc Boyer
    Nov 7, 2005
  3. Ravikiran

    Zero Optimization and Sign Optimization???

    Ravikiran, Nov 17, 2008, in forum: C Programming
    Replies:
    22
    Views:
    839
    Thad Smith
    Nov 24, 2008
  4. felipemartinsss

    Optimization Level -O2 in gcc

    felipemartinsss, Jan 11, 2009, in forum: C Programming
    Replies:
    7
    Views:
    1,243
    felipemartinsss
    Jan 12, 2009
  5. Markus Fischer
    Replies:
    1
    Views:
    365
    Markus Fischer
    May 31, 2011
Loading...

Share This Page