problem with assignment to output pin

[jonathan castro]

good morning, well,
I have a problem with the assigments of asignal to an ouput pin, the signal ACUMULADOR start in 1111111 but when I change it, and assign it to OUTDEVOLUCION in the simulation OUTDEVOLUCION appears undetermined (there are pins with xxxx). Anybody know how to fix this?
Thanks for the help

library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity dispensador is

port(

clk : in std_logic; --entrada de reloj

devolucion : in bit; --solicitar devolucion del producto

outdevolucion : out std_logic_vector(5 downto 0) --
);
end entity;

architecture arc_dispensador of dispensador is

signal acumulador: std_logic_vector(5 downto 0) := "111111";
--signal temp: u(5 downto 0) := "111111";

BEGIN
PROCESS (clk, devolucion)
BEGIN
if devolucion = '1' then
acumulador<= acumulador-"100100";
outdevolucion<=acumulador;
else
--acumulador<=acumulador-"011111";
outdevolucion<=acumulador;

end if;
end process;
end architecture;

 

[jeppe]

library ieee;
   USE ieee.std_logic_1164.ALL;
   USE ieee.std_logic_arith.ALL;
   use ieee.numeric_std.all;
  use ieee.std_logic_unsigned.all;

entity dispensador is
   port(
        clk : in std_logic; --entrada de reloj
        devolucion : in bit; --solicitar devolucion del producto
        outdevolucion : out std_logic_vector(5 downto 0) --
          );
end entity; 

architecture arc_dispensador of dispensador is 
    signal acumulador: std_logic_vector(5 downto 0) := "111111";
    --signal temp: u(5 downto 0) := "111111";

BEGIN 
     PROCESS (clk, devolucion, ACUMULADOR)
     BEGIN 
          if devolucion = '1' then 
              acumulador   <= acumulador-"100100";
              outdevolucion<=acumulador;
         else
              --acumulador<=acumulador-"011111";
              outdevolucion<=acumulador;
         end if;
      end process;
end architecture;

Try this - you need an extra signal in the sencitivitylist
Your welcome
Jeppe

 

[jonathan castro]

thanks for the help, but I still have a problem

when I assing directly ACUMULADOR to OUTDEVOLUCION i dont have problem, but when I substract or add a binary number, and then assing it (acumulador) to OUTDEVOLUCION I have the same problem (there are bits unnasigned).

another thing, the problem is when I add o substract '1', if I add '0' the OUTDEVOLUCION out well

here is a pic of example

here is the simulation when I add "000010" to acumulador, the pic show that starting from the second bit (1) the bits appear with XXXXXX

http://img106.imageshack.us/my.php?image=buenoas0.jpg


here is a second simulation but adding "000000" to acumulador, OUTDEVOLUCION outs well

http://img123.imageshack.us/my.php?image=maloct1.jpg


thanks for the help, this is urgent

 

[jonathan castro]

nobody help me?

 

[jeppe]

Well I need the code instead of a simulation jpg-view.

You must understand that a signal won't get its value immediate when used in a process.
Use variables instead or make sure that the sensitivity list correctly updated - you could be forced to used more the one process as well - one for the combinatorial logic and one for the F/F's (a Clk driven process)

 

[jonathan castro]

I used variables too, but I have the same problem

this is de code


library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity dispensador is
port(
clk : in std_logic; --entrada de reloj
devolucion : in bit; --solicitar devolucion del producto
outdevolucion : out std_logic_vector(5 downto 0) --
);
end entity;

architecture arc_dispensador of dispensador is
signal acumulador: std_logic_vector(5 downto 0) := "111111";
--signal temp: u(5 downto 0) := "111111";

BEGIN
PROCESS (clk, devolucion, ACUMULADOR)
BEGIN
if devolucion = '1' then
acumulador <= acumulador-"100100";
outdevolucion<=acumulador;
else
--acumulador<=acumulador-"011111";
outdevolucion<=acumulador;
end if;
end process;
end architecture;