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in the following code I got the exact results I want in simulation, and check syntax doesn't give me any errors, but the problem is in synthesis-it fails.
I'd appreciate any help
and thanks in advance
here is the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Div is
Generic(N:std_logic_vector(10 downto 0):="00000001000");
Port ( L2 : in STD_LOGIC_VECTOR (3 downto 0);
b1,b2 : out STD_LOGIC_VECTOR (10 downto 0);
clk,start : in STD_LOGIC);
end Div;
architecture Behavioral of Div is
----------test------
signal L_pre:STD_LOGIC_VECTOR (3 downto 0);--proven test
-------------------
begin
process(clk,start)
variable x:integer;
variable y:std_logic_vector(10 downto 0):=N;
begin
if start'event and start='0' then---------------
b1<='0'&N(10 downto 1);------------
else-------------------------
x:=conv_integer(L2);
If L_pre/=L2 then -------------rising_edge(clk)--end proven test
If L2="0000" then
y:=N;
b1<=y;
else
loop1:for i in 1 to 11 loop
If (x/=0) then
y:='0'&y(10 downto 1);
x:=x-1;
else null;
End If;
End Loop;
b1<=y;
b2<=y(9 downto 0)&'0';
y:=N;
End If;
End If;
------------test-----------
L_pre<=L2;-----end proven test
---------------------
end if;-------------------
End Process;
end Behavioral;
I'd appreciate any help
and thanks in advance
here is the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Div is
Generic(N:std_logic_vector(10 downto 0):="00000001000");
Port ( L2 : in STD_LOGIC_VECTOR (3 downto 0);
b1,b2 : out STD_LOGIC_VECTOR (10 downto 0);
clk,start : in STD_LOGIC);
end Div;
architecture Behavioral of Div is
----------test------
signal L_pre:STD_LOGIC_VECTOR (3 downto 0);--proven test
-------------------
begin
process(clk,start)
variable x:integer;
variable y:std_logic_vector(10 downto 0):=N;
begin
if start'event and start='0' then---------------
b1<='0'&N(10 downto 1);------------
else-------------------------
x:=conv_integer(L2);
If L_pre/=L2 then -------------rising_edge(clk)--end proven test
If L2="0000" then
y:=N;
b1<=y;
else
loop1:for i in 1 to 11 loop
If (x/=0) then
y:='0'&y(10 downto 1);
x:=x-1;
else null;
End If;
End Loop;
b1<=y;
b2<=y(9 downto 0)&'0';
y:=N;
End If;
End If;
------------test-----------
L_pre<=L2;-----end proven test
---------------------
end if;-------------------
End Process;
end Behavioral;