problem with libraries?

[daveip]

got an issue with the size of my "std_logic_vector"

here's the component:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.Numeric_STD.all;

entity statemachine is
    port( 
        clock : in std_logic;
        reset : in std_logic;
        in_pin : in std_logic;
        out_pin: in std_logic;
        empty : out std_logic;
        full : out std_logic;
        err : out std_logic;
        number : out std_logic_vector (9 downto 0)
        );
    end;

the design compiles fine ... but when i go to start simulation fatal error occurs and error points to this line :

number : out std_logic_vector (9 downto 0)

uh ... i have no idea why? it was (7 downto 0) before but the design requires that i count up to 1024 and not 256.

Any comments would be very much appreciated! thanks!

 

[scottcarl]

Post your code and you might get some help.