problem with loop statement

Discussion in 'VHDL' started by bxbxb3, Mar 18, 2005.

  1. bxbxb3

    bxbxb3 Guest

    Hi,
    Could anyone help me out with this probelm? When ever I try to simulate
    the code shown below, my ModelSIM hangs up!

    My code is a simple one.

    process(clk)
    begin
    if(clk'event and clk='1') then
    if reset='1' then
    reg<="000000000000000000000000000000000"; --reg is 33 bits wide(32
    downto 0)
    generator<="100000100110000010001110110110111"; --total 33 bits
    counter<=0;
    else
    while(not(counter=63)) loop
    reg<=reg(31 downto 0) & '0';
    if(reg(31)='1') then
    reg<=reg xor generator;
    end if;
    end loop;
    end if;
    end if;
    end process;
    bxbxb3, Mar 18, 2005
    #1
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  2. bxbxb3

    bxbxb3 Guest

    Sorry, I forgot to mention
    counter<=counter+1; after "end if" statement in the while loop.
    Thanks.
    bxbxb3, Mar 18, 2005
    #2
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  3. bxbxb3

    Jezwold Guest

    The problem is in the fact that you are trying to shift 'reg' left 63
    times on the rising edge of the clk signal I would have thought.
    Jezwold, Mar 18, 2005
    #3
  4. bxbxb3

    Jezwold Guest

    Well o.k 64 times.
    Jezwold, Mar 18, 2005
    #4
  5. bxbxb3

    ALuPin Guest

    You are trying to increment the SIGNAL counter in a loop within
    one clock cycle! You need one VARIABLE.



    process(clk)
    variable counter : integer range 0 to 63
    begin
    if rising_edge(clk) then
    if reset='1' then
    reg <="000000000000000000000000000000000";
    generator <="100000100110000010001110110110111";
    else
    counter := 0;
    while(not(counter=63)) loop
    reg <= reg(31 downto 0) & '0';
    if reg(31)='1' then
    reg <= (reg xor generator);
    end if;
    counter := counter+1;
    end loop;
    end if;
    end if;
    end process;

    You should always remeber that the change of a signal in one clock cycle
    only takes effect one clock cycle later!

    What are you trying to implement ?

    Rgds
    André
    ALuPin, Mar 18, 2005
    #5
  6. bxbxb3

    Jezwold Guest

    The fact is he is trying to do lots of stuff within one clock cycle.
    Jezwold, Mar 18, 2005
    #6
  7. bxbxb3

    bxbxb3 Guest

    Got it! I must not do so many shifts in a signal clock tick. Actually I
    thought the counter in the while loop would increment every clock cycle.
    Thanks for the advice.
    bxbxb3, Mar 18, 2005
    #7
  8. bxbxb3

    bxbxb3 Guest

    Actually I was trying to develop a code for 32-bit serial CRC generation. I
    tried the recommended one and was just checking other methods to do the
    same. One of the codes looks like this:

    process(clk)
    begin
    if(clk'event and clk='1') then
    if(init='1') then
    i<=63;
    j<=31;
    reg<=data_in & "00000000000000000000000000000000";
    generator_poly<="100000100110000010001110110110111";
    elsif(init='0') then
    i<=i-1;
    j<=j-1;
    if(reg(i)='1' and i>31) then
    reg(i downto j)<=reg(i downto j) xor generator_poly;
    elsif(i=31) then
    i<=63;
    j<=31;
    crc_out<=reg(31 downto 0);
    end if;
    end if;
    end if;
    end process;

    The above code does not synthesis because of (i downto j) clause.
    bxbxb3, Mar 18, 2005
    #8
  9. "bxbxb3" <> wrote in message news:<>...
    > Hi,
    > Could anyone help me out with this probelm? When ever I try to simulate
    > the code shown below, my ModelSIM hangs up!
    >
    > My code is a simple one.
    >
    > process(clk)
    > begin
    > if(clk'event and clk='1') then
    > if reset='1' then
    > reg<="000000000000000000000000000000000"; --reg is 33 bits wide(32
    > downto 0)
    > generator<="100000100110000010001110110110111"; --total 33 bits
    > counter<=0;
    > else
    > while(not(counter=63)) loop
    > reg<=reg(31 downto 0) & '0';
    > if(reg(31)='1') then
    > reg<=reg xor generator;
    > end if;
    > end loop;
    > end if;
    > end if;
    > end process;


    Hi,

    Lets say your counter does not equal 63. Then you have (I believe) an
    endless loop executing reg <= reg(31 downto 0) & '0';
    Why not try a FOR LOOP instead?

    Another suggestion: reg could be cleared with reg <= (others => '0');

    /Peter
    Peter Hermansson, Mar 18, 2005
    #9
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