Problem with simulation

Discussion in 'VHDL' started by fresh, Nov 27, 2007.

  1. fresh

    fresh

    Joined:
    Nov 27, 2007
    Messages:
    1
    Hallo

    I have a problem with a simulation in Modelsim! It always shows me the following error:

    # ** Error: (vsim-3601) Iteration limit reached at time 0 ps.

    I know what this mean but idont see the error in the Code. So i think it is possible that somebody here will see the mistake!


    entity transmit_unit is

    port (
    clk : in std_logic;
    reset : in std_logic;
    data_in : in transmit_data;
    enable_out : out std_logic := '1';
    data_out : out std_logic);

    end transmit_unit;


    architecture twoproc of transmit_unit is

    signal r, rin : transmit_reg_type;
    signal tmp_data_in : std_logic := '1';
    begin -- twoproc


    -- purpose: combinatorial process of the two-process design
    -- type : combinational
    -- inputs : data_in, r
    -- outputs: data_out, rin
    comb: process(data_in.transmit_en, r)
    variable tmp : transmit_reg_type;
    variable databit : std_logic := '0';
    variable prebit : std_logic := '0';
    begin -- process comb
    tmp := r;
    if data_in.transmit_en = '1' then
    if (tmp.precount = precount_value) then
    databit := data_in.data;
    --look if bit Stuffing is enable
    if (data_in.bit_stuff_en = '1') then
    --send the data or the stuffing bit
    if(tmp.bitnumber = conv_std_logic_vector(6,3)) then
    databit := not prebit;
    enable_out <= '1';
    tmp.bitnumber := (others => '0');
    else
    prebit := databit;
    end if;
    --compare if the the prebit and the databit are the same
    if (databit = prebit) then
    tmp.bitnumber := tmp.bitnumber + 1;
    else
    tmp.bitnumber := (others => '0');
    end if;
    --control the bitnumber if it reached the value 5
    if (tmp.bitnumber = bitstuffing_value) then
    enable_out <= '0';
    tmp.bitnumber := conv_std_logic_vector(6,3);
    end if;
    end if;

    tmp_data_in <= databit;
    tmp.precount := (others => '0');
    else
    tmp.precount := tmp.precount + 1;
    end if;
    else
    tmp.precount := precount_value;
    end if;
    rin <= tmp;
    end process comb;

    data_out <= tmp_data_in;

    -- purpose: sequential process or the two-process design
    -- type : sequential
    -- inputs : clk, reset, rin
    -- outputs: r
    seq: process (clk, reset)
    begin -- process seq
    if reset = '0' then -- asynchronous reset (active
    low)
    r.bitnumber <= (others => '0');
    r.precount <= precount_value;
    elsif clk'event and clk = '1' then -- rising clock edge
    r <= rin;
    end if;
    end process seq;

    end twoproc;
     
    fresh, Nov 27, 2007
    #1
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  2. fresh

    bedrr

    Joined:
    Nov 22, 2007
    Messages:
    5
    Location:
    morocco




    can you explain what the types transmit_data, transmit_reg_type are ?
     
    bedrr, Nov 28, 2007
    #2
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