Queston about addition in Maxplus II

[lezah]

Hi,
I encounter some question about addition in Maxplus II,
Some addition result is wrong. A,B,D in either signed or
std_logic_vector are wrong. What is the problem?
Thanks

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;

entity test1 is
port(
clk :in std_logic;
A :in signed(4 downto 0);
B :in signed(4 downto 0);
D ut signed(5 downto 0)
);
end test1;
architecture behave of test1 is
begin
process(clk)
begin
if falling_edge(clk) then
D<=A+B;
end if;
end process;
end behave;

 

[Jonathan Bromley]

Hi,
I encounter some question about addition in Maxplus II,
Some addition result is wrong. A,B,D in either signed or
std_logic_vector are wrong. What is the problem?
Thanks

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;

entity test1 is
port(
clk :in std_logic;
A :in signed(4 downto 0);
B :in signed(4 downto 0);
D ut signed(5 downto 0)
);
[...]

D<=A+B;

[...]

A and B are both 5-bit vectors, and the addition will return a
5-bit result. This result cannot be copied to the 6-bit target D.

I guess you want to preserve the carry bit. In this case you must
do 6-bit arithmetic. This you do by sign-extending either or both
of A, B because std_logic_arith."+" returns a value as wide as its
wider operand.

The usual solution would be

D <= A + signed'(B(4) & B);

or, if you wished to be pedantic, you could sign-extend BOTH
operands:

D <= signed'(A(4) & A) + signed'(B(4) & B);

Alternatively you may wish to throw away the carry bit:

D(4 downto 0) <= A + B;

but in that case you need to decide rather carefully what
you want to happen to D(5).
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Ralf Hildebrandt]

I encounter some question about addition in Maxplus II,
Some addition result is wrong. A,B,D in either signed or
std_logic_vector are wrong. What is the problem?
Thanks

library IEEE;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;

Don't use these 2 libraries, because the implementation of the packages
differs on different platforms.

use IEEE.Numeric_std.all;

instead.

entity test1 is
port(
clk :in std_logic;
A :in signed(4 downto 0);
B :in signed(4 downto 0);
D ut signed(5 downto 0)
);
....
D<=A+B;

The main problem is the different bit width of both summands and result.
Use the same bitdwidth for "D" too (if you don't need the carry-out) or

D<= resize(A,6) + resize(B,6);


The function "resize" is defined in IEEE.numerc_std.all. A similar
function may be provided by your libraries.
"Resize" got 2 arguments: the signal to resize and the number of bits of
the result (6 in our case).


An other way (manually expanding a signed number 1 Bit) would be

D<= (A(A'high) & A) + (B(B'high) & B);


A'high results the position of the MSB of A (in our case: 4).
A(A'high) is the MSB (in our case: A(4) )
The & Operator concatenates bits and vectors.



Ralf

 

[Jonathan Bromley]

D <= (A(A'high) & A) + (B(B'high) & B);

I think I'd prefer A'left, Ralf

But it's still prettier than the simple solution I offered.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

use IEEE.Numeric_std.all;

The main problem is the different bit width of both summands and result.
Use the same bitdwidth for "D" too (if you don't need the carry-out) or

D<= resize(A,6) + resize(B,6);

Yes. I like this method.
Add some generics and you have:

----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test1 is -- Mike Treseler Mon Mar 1 13:27:16 2004
generic (result_len : natural := 6;
add_len : natural := 5);
port(
clk : in std_logic;
A : in signed(add_len-1 downto 0);
B : in signed(add_len-1 downto 0);
D : out signed(result_len-1 downto 0)
);
end test1;
architecture behave of test1 is

begin
clked : process(clk) is
begin
if rising_edge(clk) then
D <= resize(A, D'length) + resize(B, D'length);
end if;
end process clked;
end behave;

-- Mike Treseler

 

[lezah]

Thanks all for your suggestions,
But my old version Maxplus II doesn't support ieee.numeric_std.all;
In fact, I would like to perform 3 addition with carry bits, eg:
D<=A+B+C;
Have you got any idea without useing the numeric_std library?
Thanks again

 

[Jonathan Bromley]

Thanks all for your suggestions,
But my old version Maxplus II doesn't support ieee.numeric_std.all;
In fact, I would like to perform 3 addition with carry bits, eg:
D<=A+B+C;
Have you got any idea without useing the numeric_std library?

The solution I posted doesn't require numeric_std
(manual sign-extension of at least one operand to
the required width). Ralf offered a cleaner version, which
also does not require numeric_std.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

But my old version Maxplus II doesn't support ieee.numeric_std.all;

Quartus has the library.
You can get it free at:
http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html

In fact, I would like to perform 3 addition with carry bits, eg:
D<=A+B+C;

then declare:

ci : in signed(0 downto 0);

and subtract ci:

D <= resize(A, D'length) + resize(B, D'length) - ci;

carry out is D(D'left)

-- Mike Treseler